S1D13742 Mobile Graphics Engine Hardware Functional Specification
This is the Hardware Functional Specification for the S1D13742 Embedded Memory LCD Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers.
1.2 Overview Description：
The S1D13742 is a color LCD graphics controller with an embedded 768K byte display buffer. The S1D13742 supports a 8/16-bit Intel 80 CPU architecture while providing high performance bandwidth into display memory allowing for fast screen updates.
Products requiring a rotated display image can take advantage of the SwivelView™ feature which provides hardware rotation of the display memory transparent to the software appli-cation. Resolutions supported include 800x480 single buffered and 352x416 double buffered.
The S1D13742 uses a double-buffer architecture to prevent any visual tearing during streaming video screen updates.
Features：
2.1 Integrated Frame Buffer：
• Embedded 768K byte SRAM display buffer.
2.2 CPU Interface：
• 8/16-bit Intel 80 interface (used for display or register data).
• Chip select is used to select device. When inactive, any input data/command will be ignored.
2.3 Input Data Formats：
• RGB: 8:8:8, 6:6:6, 5:6:5 (8:8:8 will be truncated to 16 or 18 bpp).
• YUV 4:2:2, 4:2:0 (Internal YUV to RGB Converter stored as 16 or 18 bpp).
Note：
All input data must be internally converted to the same format before being stored in the display buffer. Different data types can not be mixed within a common display buffer.
2.4 Display Support：
• Active Matrix TFT interface.
• 18/36-bit interface.
• Supports resolutions up to 800x480.
2.5 Display Modes：
• 16/18 bit-per-pixel (bpp) color depths.
• 16 bpp to 18 bpp conversion: Input data can be converted from 16 bpp to 18 bpp in one of three ways.
1. RGB (5:6:5) msb copying to create new lsb for the Red and Blue components. This conversion is done prior to storing in memory, as this allows for 16 bpp and 18 bpp input data to be mixed.
2. Gamma Correction Look-Up-Tables: there are three, 64 position, 8-bit wide LUT’s. The data stored in memory can be used as an index into these tables. The LUT’s are placed on the display side and therefore do not affect the data stored in memory.
3. RGB (5:6:5) stored in memory: LUT is by-passed. Copy msb to lsb for red and blue during the display read from memory.
2.6 Display Features：
• All display writes will be handled by window apertures/position for complete or partial display updates. All window coordinates are referenced to top left corner of the displayed image (even in a rotated display, the top-left corner is maintained and no host side translation need take place).
• SwivelView™: 90°, 180°, 270° counter-clockwise hardware rotation of display image. All displayed windows can have independent rotation. No additional programming necessary when enabling these modes.
• Double-Buffer available to prevent image tearing during streaming input. Resolutions supported must fit inside 384K bytes (½ of total available display buffer). Typical reso-lution of 352x416.
• Pixel Doubling: Horizontal and Vertical averaging for smooth doubling of a single window.
• Pixel Halving: no limitation on number of windows.
2.7 Clock Source：
• Internal programmable PLL.
• Single MHz clock input: CLKI.
• CLKI available as CLKOUT (separate CLKOUTEN pin associated with output).
• output state = 0 when disabled.
2.8 Miscellaneous：
• Hardware / Software Power Save mode.
• Input pin to Enable/Disable Power Save Mode.
• General Purpose Input/Output pins are available (GPIO[7:0]).
• INT pin associated with selectable GPIO inputs.
• Package: QFP20 144-pin package
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User's Guide |
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Please see the document for details |
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QFP20 |
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English Chinese Chinese and English Japanese |
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March 15, 2018 |
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Rev. 6.6 |
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X63A-A-001-06.6 |
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3 MB |
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