EZAIRO 7111 HYBRID Audio Processor for Digital Hearing Aids
■Ezairo® 7111 is an open−programmable DSP−based hybrid specifically designed for use in high−performance hearing aid and hearing implant devices. The Ezairo 7111 hybrid includes the Ezairo 7100 System−on−Chip (SoC), with its high−precision quad−core architecture that delivers 375 MIPS, without sacrificing power consumption.
■The highly integrated Ezairo 7100 includes an optimized, dual−Harvard CFX Digital Signal Processor (DSP) core and HEAR Configurable Accelerator signal processing engine. It also features an Arm® Cortex®−M3 Processor Subsystem that supports various types of protocols for wireless communication. This block combines an open−programmable controller with hardware accelerators for audio coding and error correction support.
■Ezairo 7100 also includes a programmable Filter Engine that enables time domain filtering and supports an ultra−low−delay audio path. When combined with non−volatile memory and wireless transceivers, Ezairo 7100 forms a complete hardware platform.
■The Ezairo 7111 hybrid contains the Ezairo 7100 SoC, 2 Mb EEPROM storage and the necessary passive components to directly interface with the transducers required in a hearing aid.
■Key Features
●Programmable Flexibility: the open−programmable DSP−based system can be customized to the specific signal processing needs of manufacturers. Algorithms and features can be modified or completely new concepts implemented without having to modify the chip.
●Fully Integrated Hybrid: includes the Ezairo 100SoC, 2 Mbit EEPROM storage and the necessary passive components to directly interface with the transducers required in a hearing aid.
●Quad−core Architecture: includes a CFX DSP, a HEAR Configurable Accelerator, an Arm Cortex−M3Processor Subsystem and a programmable Filter Engine. The system also includes an efficient input/output controller (IOC), system memories, input and output stages along with a full complement of peripherals and interfaces.
●CFX DSP: a highly cycle−efficient, programmable core that uses a 24−bit fixed−point, dual−MAC, dual−Harvard architecture.
●HEAR Configurable Accelerator: a highly optimized signal processing engine designed to perform common signal processing operations and complex standard filter banks.
●Arm Cortex−M3 Processor Subsystem: a complete subsystem that supports efficient data transfer to and from a wireless transceiver. The subsystem includes hardwired CODECS (G.722, CVSD) and Error Correction support (Reed−Solomon, Hamming), as well as a fully programmable Arm Cortex−M3 processor and dedicated interfaces. It is compatible with various wireless technologies (NFMI, RF).
●Programmable Filter Engine: a filtering system that allows applying a various range of pre− or post−processing filtering, such as IIR, FIR and biquad filters.
●Configurable System Clock Speeds: 1.28 MHz,1.92 MHz, 2.56 MHz, 3.84 MHz, 5.12 MHz, 6.4 MHz,7.68 MHz, 8.96 MHz, 9.60 MHz, 10.24 MHz* (default clock calibration), 12.80 MHz and 15.36 MHz to optimize the computing performance versus power consumption ratio. The calibration for these 12 clock speeds are stored in the manufacturing area of the EEPROM.
●Ultra−low Delay: programmable Filter Engine supports an ultra−low−delay audio path of 0.044 ms(44 s) for superior performance of features such as occlusion management.
●Ultra−high Fidelity: 85 dB system dynamic range with up to 110 dB input signal dynamic range, exceptionally−low system noise and low group delay.
●Ultra−low Power Consumption: <0.7 mA @10.24 MHz system clock (executing a tight MAC−loop in the CFX DSP core plus a typical hearing aid filter bank on the HEAR Configurable Accelerator).
●High Output Level: output levels of ~139 dB SPL possible with low impedance receiver (measured using IEC 711 coupler).
●Diverse Memory Architecture: a total of 40 k words of program memory and 44 k words of data memory, shared between the four cores included on the Ezairo 7100 chip.
●Data Security: sensitive program data can be encrypted for storage in EEPROM to prevent unauthorized parties from gaining access to proprietary algorithm intellectual property.
●Signal Detection Unit: ultra−low−power detection system for signals on any analog inputs.
●High Throughput Communication Interface: fastI2C−based interface for quick download, debugging and general communication.
●Highly Configurable Interfaces: two PCM interfaces, two I2C interfaces, two SPI interfaces, a UART interface as well as multiple GPIOs can be used to stream configuration, control or signal data into and out of the Ezairo 7111 hybrid.
●On−chip PLL: support for communication synchronization with wireless transceiver.
●Glueless MMI: link to various analog and digital user interfaces such as analog or digital volume control potentiometers, push buttons for program selection and microphone/telecoil switching.
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Datasheet |
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Please see the document for details |
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SIP19 |
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English Chinese Chinese and English Japanese |
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November, 2018 |
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Rev. 1 |
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E7111/D |
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514 KB |
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