AS4C8M16S 128Mb/ 8M x 16 bit Synchronous DRAM (SDRAM) Data Sheet
DRAM containing 128 Mbits. It is internally configured as 4
Banks of 2M word x 16 DRAM with a synchronous interface
(all signals are registered on the positive edge of the clock
signal, CLK) . Read and write accesses to the SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration
of a BankActivate command which is then followed by a
Read or Write command.
The AS4C8M16S provides for programmable Read or
Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be
enabled to provide a self- timed row precharge that is
initiated at the end of the burst sequence. The refresh
functions, either Auto or Self Refresh are easy to use.
By having a programmable mode register, the system
can choose the most suitable modes to maximize its
performance. These devices are well suited for applications
requiring high memory bandwidth and particularly well
suited to high performance PC applications.
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AS4C8M16S 、 AS4C8M16S -6TCN 、 AS4C8M16S-6TIN 、 AS4C8M16S -7TCN 、 AS4C8M16S-7BCN 、 AS4C8M16S-6BIN 、 AS4C8M16S-6TCN 、 AS4C8M16S-7TCN |
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Datasheet |
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Halogen free 、 Lead Free 、 Pb free 、 RoHS |
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Please see the document for details |
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Commercial 、 Industrial |
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TSOP II;TFBGA |
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English Chinese Chinese and English Japanese |
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FEBRUARY 2011 |
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4.5 MB |
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