MPC866 PowerQUICC™ Family
■Freescale Semiconductor’s PowerQUICC™ MPC866 family is designed to deliver a versatile, single-chip integrated processor and peripheral combination that can be used in a variety of controller applications—excelling particularly in communications and networking products. Like the MPC862, the MPC866 family (including the MPC859T and MPC859DSL) is engineered to deliver simultaneous Fast Ethernet (MII) and Parallel ATM (UTOPIA) operation, UTOPIA II Multi-PHY, UTOPIA Slave, AAL2, VBR and port-to-port switching. Freescale’s leading PowerQUICC architecture integrates two processing subsystems. One is built around the 8xx core, which is instruction set compatible with other processors built on Power Architecture™ technology. The second is the communications processor module (CPM). The CPM is a dedicated RISC-based communications engine designed to support four serial communications controllers (SCCs), providing a total of eight serial channels: four SCCs, two serial management controllers (SMCs), one serial peripheral interface (SPI) and one inter-integrated circuit (I2C) interface. This dual-processor architecture is designed to provide superior performance over traditional architectures because the CPM offloads communications intensive processing from the embedded 8xx core. This partitioning frees up the 8xx core to perform other system functions.
●Power Architecture technologyEmbedded 8xx core
●4 KB instruction cache
●4 KB data cache
●16 KB instruction cache in MPC866P
●8 KB data cache available in MPC866P
●Powerful memory controller and system functions
●Efficient architecture that involves a separate RISC processor CPM for handling communications
●Up to four SCCs
●Support for Ethernet, Fast Ethernet, HDLC, asynchronous transfer mode (ATM) and more
●Enhanced ATM functionality
●Two SMCs, one SPI and one I2C
● Many other features—timers, baud rate generators, etc.
●8K dual-port RAM
●Available in a 357-pin RoHS compliant BGA package; MPC866 and MPC859T available at 100 and 133 MHz; MPC859DSL available at 50 and 66 MHz
●Strong third-party tools support through Freescale’s Design Alliance Program4
●0.18μ technology
●1.8V core, 3.3V I/O
■Embedded 8xx microprocessor core providing 176 MIPS (using Dhrystone 2.1) at 133 MHz
◆Single-issue, 32-bit version of the embedded 8xx core with 32- x 32-bit fixed point registers
◆4 KB instruction cache and 4 KB data cache (16 KB instruction cache and 8 KB data cache available in 866P)
◆Memory management units with 32-entry TLBs and fully associative instruction and data TLBs
■ Advanced on-chip emulation debug mode
■Data bus dynamic bus sizing for 8-, 16- and 32-bit buses
■Communications processor module
◆32-bit scaler RISC controller
◆Two serial management controllers
◆16 serial DMA (SDMA) channels
◆One I2C port
◆One serial peripheral interface
◆Four general-purpose timers
◆Time-slot assigner Interrupts
◆Four baud rate generators
◆Enhanced ATM Functionality
▲Simultaneous Fast Ethernet (MII) and parallel ATM operation
▲UTOPIA II Multi-PHY and
▲UTOPIA Slave
▲AAL2 and VBR microcode in ROM··
▲ATM port-to-port switching
◆Protocols supported··
▲Ethernet IEEE® 802.3 and MII··
▲ATM
▲HDLC
▲Asynchronous HDLC
▲Channelized HDLC
▲Multi-channel HDLC
▲AppleTalk®
▲UART
▲IrDA
▲Basic Rate ISDN (BRI)
▲Primary Rate ISDN (PRI)
▲Totally transparent mode with/without CRC
■System integration unit
◆Memory controller
◆Real-time clock
◆PCMCIA interface
◆System functions
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Integrated Communications Processors 、 single-chip integrated processor |
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[ controller applications ][ communications ][ networking product ][ DSLAMs ][ SOHO and enterprise routers ][ Remote access servers ][ Wireless base stations ][ ISDN equipment ][ xDSL equipment ][ ATM switches ][ Telecom switching ][ transmission devices ][ Integrated access devices ][ Cable modems ][ DSL modems ][ T1/E1 termination equipment ][ LAN switches ][ Wireless LA ] |
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2019/04/17 |
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REV 4 |
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MPC866FACT |
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185 KB |
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