Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
|
|
|
|
|
|
|
User's Guide |
|
|
|
|
Please see the document for details |
|
|
|
|
|
|
|
|
|
|
|
English Chinese Chinese and English Japanese |
|
|
June 2017 |
|
|
Version 2017.06.16 |
|
|
UG-01087 |
|
|
329 KB |
- +1 Like
- Add to Favorites
Recommend
- Efficient Power Conversion (EPC) Expands 100 V eGaN FET Family Offering Designers Best-in-Class Performance and Cost for 48 V DC-DC Conversion
- How to Design A Power Factor Correction (PFC) 400 V Rectifier Using 200 V eGaN® FETs
- New 600 A, 300+ kVA flowANPC S3 split for 1500 V solar inverter
- EPC Expands High-Performance eGaN FET Product Family with Latest 80 V and 200 V Offerings
- Diotec Ultrafast Rectifier US1M——Why It Makes Sense to Use a 1000 V Component on a 24 V Smart Building Field Bus System？
- R1260 Series 60 V Input/Synchronous Buck DC/DC Converter Controller offers maximum design flexibility
- Higher Performance 600 V flowPIM 1 + PFC Modules for up to 8 kW, PIM with Two-leg/three-leg Interleaved PFC Circuit
- Geehy’s G32A1445 Automotive General-Purpose MCU Certified by TÜV Rheinland for ISO 26262 ASIL-B
All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.
Integrated Circuits
Discrete Components
Connectors & Structural Components
Assembly UnitModules & Accessories
Power Supplies & Power Modules
Electronic Materials
Instrumentation & Test Kit
Electrical Tools & Materials
Mechatronics
Processing & Customization
