Extraction of Parasitic Capacitance for Multilayer Chip Ceramic Inductor
Chip inductor can be classified as wire wound type and multilayer type on the basis of the electrode coil formation type. The former is the extending product of traditional wire wound inductor and is hard to downsize. However, multilayer chip inductor is made by casting ceramic slurry, printing silver paste, and co-firing to form closed magnetic loop. The advanced thick-film screen printing technology and multilayer proceeding technology achieve miniaturization and SMT. Therefore, multilayer chip inductor is the paramount focus in inductor industry.
Due to the high frequency design tendency of the electronics products, the influence effect of parasitic parameters on circuit becomes more and more serious. Compared with traditional wire wound type, multilayer chip inductor has larger parasitic capacitance which is the key factor of low self-resonance frequency (S.R.F.) and thus is limited for high frequency application.
When working at low frequency, multilayer chip inductor is equivalent to the series circuit of an inductor and a low resistance resistor. As the work frequency increasing, the capacitance effect among the electrode layers becomes obvious and the inductor equals to an inductor in series with a resistor, and then in parallel with a capacitor. The inductor behaves high resistance at SRF due to the counterbalance of inductive reactance and capacitive reactance. While at higher frequency than SRF, the inductor behaves capacitive effect. We can see the performance of multilayer chip inductor at high frequency completely depends on its parasitic capacitance, which is comprised of stray capacitance among internal electrode layers and stray capacitance between internal electrodes and terminal electrodes. Therefore，it is significant for design and simulation of inductor to extract the parasitic capacitance by an easy and effective method. Commonly, there are three methods, which are analytical method, test method and numerical method.
Analytical method is an approximate method to obtain capacitance based on dividing the entire space into lots of units. Every unit is small enough to be treated as uniform electric field, and then the capacitance of each unit can be calculated by the formula of parallel plate capacitor. Actually, it is a complicated method.
Test method is a deduction method by measuring the inductance and the SRF. However, due to skin effect, the inductance at SRF is very different from that at low frequency and it is necessary to figure out an accurate inductance. This method is heavily depended on the precision of measurement and calculation, and can be only used as validation for calculation value.
As a numerical method, Finite Element Method (FEM) is an effective method to solve engineering problem. Specifically, first we need to get the physical and geometric parameters of the ceramic and electrode of multilayer chip inductor; and then we establish a 3D finite element module of the inductor using Ansoft Q3D software; finally, the parasitic capacitance can be calculated by operating capacitor matrix among electrodes. This method can obtain accurate result and is applied in inductor design.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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Aug. 2010 |
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205 KB |
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