74LVC1G04 Single inverter
●The 74LVC1G04 provides one inverting buffer.
●Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.
●Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall time.
●This device is fully specified for partial power-down applications using I-OFF. The I-OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
●Features and benefits:
■Wide supply voltage range from 1.65 V to 5.5 V
■5 V tolerant inputs for interfacing with 5 V logic
■High noise immunity
■Complies with JEDEC standard:
▲JESD8-7 (1.65 V to 1.95 V)
▲JESD8-5 (2.3 V to 2.7 V)
▲JESD8-B/JESD36 (2.7 V to 3.6 V)
■ESD protection:
▲HBM: ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V
▲MM: JESD22-A115-A exceeds 200 V
■±24 mA output drive (V
■CMOS low power consumption
■Latch-up performance exceeds 250 mA
■Direct interface with TTL levels
■Inputs accept voltages up to 5 V
■Multiple package options
■Specified from -40 °C to +85 °C and -40 °C to +125 °C.
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74LVC1G04 、 74LVC1G04GW 、 74LVC1G04GV 、 74LVC1G04GM 、 74LVC1G04GF 、 74LVC1G04GN 、 74LVC1G04GS 、 74LVC1G04GX 、 74LVC1G04GX4 |
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Datasheet |
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Please see the document for details |
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SOT1269-2;SOT1226;SOT1202;SOT1115;SOT891;SOT886;SOT753;SOT353-1 |
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English Chinese Chinese and English Japanese |
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8 June 2018 |
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Rev. 15 |
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74LVC1G04 |
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698 KB |
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