CrossStream Application Notes
●INTRODUCTION
■The CrossStream chip set is a high-performance serial backplane solution that runs at 2.125 Gbps. It is word synchronous across all port cards and can be scaled in multiples of 32 Gbps. The guidelines and simulations described in this document are based on 2.5 Gbps as a worst-case.
■The maxim that must be followed when designing gigabit systems is that the system, as a whole,must be considered from day one. It seems self evident, but the repercussions of early decisions will have a much more far-reaching effect in dollars and time at 2.5 Gbps than at 100 MHz. As a result, it is important to understand the implications of the individual interconnect issues and how they work in concert to produce a fully functional first article system with an acceptable bit error rate (BER).
■As signals approach the GHz range, it is imperative to account for frequency-dependent attenuation of the signal due to skin effect and dielectric losses. At speeds greater than several hundred megahertz, the majority of the electrical energy travels on the surface of the trace.Thus, the total surface area of a trace’s cross-section needs to be maximized to reduce the attenuation of the signal that will occur over the entire length of the signal interconnect. This loss reduces the signal amplitude and slows the edge speed, thus yielding a smaller “eye” that is more susceptible to jitter induced errors. The traces need to be wide enough to control losses as a function of the specific logic requirements, interconnect length and frequency. This means that backplanes optimized to run at 500 MHz will likely not be able to support 1.5 GHz signals. If a speed upgrade is anticipated, the original design must be based on the fastest frequency. So, if you're designing a 1.2 Gbps system but want the same backplane for the next generation at 2.5 Gbps, the 1.2 Gbps system must be able to absorb the inherently higher costs of the 2.5 Gbps requirement.
■The intent of this application note is to provide realistic, real world guidance in implementing the CrossStream 2.5 Gbps link on FR4 boards. It cannot address the uniqueness and individual requirements of each design. SPICE simulations of specific implementations are strongly encouraged. SPICE models for the CrossStream I/O and HS3 connector models are available on request. Both AMP and Vitesse are also available to work closely with you on the design to ensure success. AMP can provide assistance regarding simulation, backplane design and manufacturing. See the Appendix for contact information.
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Supplier and Product Introduction |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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July 30, 1999 |
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Revision 0.5 |
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98060A-5 |
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698 KB |
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