Broadcom Ltd.
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ACPL-W346
Evaluation Kit
Evaluation Kit Overview
Figure 2 KIT8020CRD8FF1217P-1 Basic Block Diagram
This reference design will describe the basic operation of using
gate drive optcoupler ACPL-W346 for the SiC MOSFET
evaluation kit. Purchase of the evaluation kit and the user's
manual are available from catalogue distributors:
http://www.digikey.sg/product-detail/en/KIT8020-CRD-8FF121
7P-1/KIT8020-CRD-8FF1217P-1-ND/5027643
http://www.mouser.sg/ProductDetail/Cree-Inc/KIT8020-CRD-8
FF1217P-1/?qs=%2fha2pyFadugoWU85a9ES3mGSyQOWKTBm
odw8qlZLPgNqDts0nlnPYD4v%252bh%2fKfVJR
Evaluation Kit Overview
Figure 3 Block Diagram with Gate Drive Optocoupler ACPL-W346
The evaluation kit uses 2 gate drive optocoupler ACPL-W346 to
drive the SiC MOSFET directly in the half bridge topology. The
ACPL-W346 is a basic gate driver optocoupler used to isolate
and drive the SiC MOSFET operating at high DC bus voltage. It
has a rail-to-rail output with 2.5A maximum output current to
provide fast switching high voltage and high driving current to
turn-on and off the SiC MOSFET efficiently and reliably. The
unique feature of ACPL-W346, is the speed and is the industry's
fastest in its class. The maximum propagation delay is 120ns
and typical rise and fall times are around 10ns. The very high
CMR, common mode rejection of 50kV/μs is required to isolate
high transient noise during the high frequency operation from
causing erroneous outputs. It can provide isolation certified by
UL1577 for up to VISO 5000VRMS/min and IEC 60747-5-5 for
working voltage, VIORM up to 1140VPEAK.
The 2W DC/DC converter with +12V VCC input generates +24V
Vcc_out output voltage with 6kVDC isolation that is supplying
voltage to ACPL-W346 on push-pull gate drive of the
secondary side as shown in Figure 3. In this circuit, a 5V zener in
parallel with 1uF capacitor is used to generate -5V Vgs voltage
for the SiC MOSFET turn-off and turn-on Vgs voltage is equal to
24V-5V=19V. Note that SiC MOSFET can be turned off with zero
voltage, and the -5V turn-off voltage helps with faster turn-off
and lower turn-off losses and also improves dv/dt induced
self-turn-on and noise immunity during transient periods with
more margin for Vgs turn-on threshold voltage.
Hardware Description and Board Design
Figure 4 Evaluation Kit Key Connectors and Components
In a synchronous phase-leg Buck converter topology, CON1
connects to the positive DC BUS rail, CON2/5 connects to the
negative BUS rail or GND and CON3 the output of the
converter. Several topologies can be configured with this
board: synchronous Buck, non-synchronous Buck (or high-side
Buck), synchronous Boost, non-synchronous Boost, half
phase-leg bridge converter, H bridge converter (2x EVL boards)
and bi-directional buck-boost converters. Please refer to the