1 of 38 June 17, 2005
© 2005 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice
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IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
Description
The 89TSF5xx is a complete switch fabric, consisting of two chips:
89TSF552 (queuing engine, 10 Gbps).
89TSF500 (crossbar and scheduler).
The 89TSF552 typically resides on a line card and the 89TSF500
usually resides on a separate switch card. An 89TSF552 connects with
the 89TSF500 through high-speed serial links.
The 89TSF5xx switch fabric has a modular and scalable architecture
that gives system designers maximum flexibility and performance. This
architecture allows a switch to be implemented either on a single shelf
using an electrical backplane or on multiple shelves connected by
optical transceivers, thus helping system vendors overcome physical
space constraints.
The 89TSF552 supports line card speeds up to OC-192 (full duplex).
It incorporates a 16-bit CSIX-over-LVDS interface to line card devices,
allowing the 89TSF5xx to operate seamlessly with the IDT 89TTM552
traffic manager, or other compatible traffic managers and network
processors.
In the ingress direction, the 89TSF552 manages a set of virtual
output queues (VOQs), negotiates the routing path through the switch
fabric, and transmits data to an 89TSF500. In the egress direction, the
89TSF552 receives data from an 89TSF500 and transmits the traffic,
through a CSIX-over-LVDS interface, either to IDT’s 89TTM552 traffic
manager or to another device (such as a network processor) on the line
card.
89TSF5xx Features
◆
Up to 32 switch ports, with 24 Gbps available per switch
port.
◆
Variable length CSIX payload (up to 132 bytes) that supports
any type of traffic.
◆
Virtual output queues (VOQs) in the ingress direction that
eliminate head-of-line blocking. The 256 unicast VOQs
provide:
– A maximum of 32 ports with 8 CoS, or
– A maximum of 16 ports with 4 subports and 4 CoS.
◆
Spatial multicast support with up to 4K global multicast
labels. Each multicast label can specify from 1 to 32 ports.
◆
Efficient backpressure mechanism that eliminates cell loss
caused by congestion.
◆
In-service scalable architecture.
◆
“Stackable” architecture. Total aggregate bandwidth is
linearly proportional to the number of 89TSF500s. Port rate
is configurable up to OC-192.
◆
Always non-blocking architecture across destination, traffic
type (cell, packet), and class of service (CoS).
◆
Supports up to 4 egress subports per switch port.
◆
Carrier class reliability features:
– Flexible architecture that allows the 89TSF switch fabric to be
employed in a single switch shelf or in multiple switch shelves.
– Automatic link diagnostics that detect faulty link connections.
– Both n+m (load-sharing mode) and 1:1 protection (active/
standby mode) on serial links.
– Patented error correction scheme to reduce the system bit
error rate by 10
5
.
– Line cord redundancy via Redundant Destination Mapping
(RDM) and Queue-Mapped Redundancy (QMR).
– Dynamic 89TSF500 rerouting that avoids congested or faulty
89TSF500s.
– Zero cell loss during controlled switchover to standby
89TSF500s.
◆
Advanced diagnostic features including multiple loopback
paths.
◆
Unicast and multicast traffic with up to 8 classes of service.
◆
Industry-standard CSIX-over-LVDS interface.
◆
Backward compatibility with IDT’s ZSF200 switch fabric.
89TSF552 Features
◆
24 embedded SerDes links per device at 2.5 Gbps per link.
◆
Virtual output queues (VOQs) that buffer data according to
destination, traffic type and class of Service (CoS).
◆
Guaranteed cell ordering.
◆
External processor interface for status and register
configuration.
◆
Support for n+m (load-sharing) and 1:1 (active/standby)
redundancy modes.
89TSF552
Preliminary Information*
Switch Fabric Data Sheet
2 of 38 June 17, 2005
IDT 89TSF552
*Notice: The information in this document is subject to change without notice
89TSF552 Functional Block Diagram
89TSF552 Pin Description
Note: Information in this section is subject to change. Contact your IDT FAE before making design decisions.
In this data sheet, direction is indicated as follows: I for In, O for Out, B for Bidirectional, and P for power.
Signal Name I/O Type Dir. Freq. Remarks
SYS_CLK (pin A21) 3.3V LVTTL I 125 MHz N/A
PLL_SYS_LCK (pin B19)
3.3V LVTTL O — N/A
PLL_RST (pin C22)
3.3V LVTTL I — N/A
PLL_DIV_RST_N (pin D22)
3.3V LVTTL I —
33K Ω internal pullup
PLL_SYS_VSSA (pin J20)
AVSS P —
33K Ω internal pullup
PLL_SYS_VDDA (pin K20)
3.3V AVDD P — Supply
PLL_SYS_VDD (pin H21)
1.8V VDD P — Supply
PLL_SYS_VSS (pin J21)
VSS P — Supply
Table 1 89TSF552 PLL Control and Power Pins
data
2.5 Gbps
SerDes
Ingress
CSIX
Receiver
(ICRX)
Egress
CSIX
Transmitter
(ECTX)
Ingress
VOQs
(IVOQ)
request
Request
Processor
(RP)
C2C
Diagnostic
Loopback
2.5 Gbps
SerDes
Egress Buffer
(EBUFF)
Processor
Interface
Processor
up to
33 MHz
125
MHz
CSIX
domain
(24)
(24)
•
•
•
(256 + 2)
To
89TSF500
•
•
•
•
•
•
CSIX
Loopback
CSIX domain: 500 MHz to 1.0 GHZ, 16 bits.
16 or 32 bits
16 or 32 bits
Egress to
IVOQ
Loopback
SerDes
line-side
loopback
SerDes
loopback