eGaN® FET DATASHEET EPC23102
The ePower
TM
Stage IC Product Family integrates input logic interface, high-side level
shiing, synchronous bootstrap charging and gate drivers along with eGaN output FETs into
one monolithic integrated-circuit using EPC’s proprietary GaN IC technology. The result is a
Power Stage IC that translates logic level control signals into a high voltage and high current
power stage that is simpler to design, smaller in size and easier to manufacture while being
more ecient to operate.
Key parameters
PARAMETER
UNIT
Power Stage Load Current (1 MHz)
A
Pulsed current (25°C, T
pulse
= 300 μs)
Operang PWM Frequency (Minimum)
kHz
Operang PWM Frequency (Maximum)
MHz
Absolute Maximum Input Voltage
V
Operang Input Voltage Range
Nominal Bias Supply Voltage
Output Current and PWM Frequency Rangs are specied at ambient temperature of 25°C. See Applicaon Informaon secon
for rang methodologies, test condions, thermal management techniques and thermal derang curves.
Device informaon
PART NUMBER
Rated R
DS(on)
for HS and LS FETs at 25 °C
QFN Package Size (mm)
EPC23102
6.6 mΩ + 6.6 mΩ
3.5 x 5
All exposed pads feature weable anks that allow side wall solder inspecon. High voltage and low voltage
pads are separated by 0.6mm spacing to meet IPC rules.
Figure 1: Performance curves
Buck converter, V
IN
= 48 V, V
OUT
= 12 V, deadme = 10 ns, L = 2.2 µH, DCR = 700 µΩ, top side heatsink
aached, airow = 500 LFM, T
A
= 25°C, using EPC90147 evaluaon board.
EPC23102 ePower
TM
Stage IC
Package size: 3.5 x 5 mm
Applicaons
• Buck, boost, buck-boost converters
• Half-bridge, full bridge LLC converters
• Motor drive inverter
• Class D audio amplier
Features
• Integrated high-side and low-side eGaN® FET with
internal gate driver and level shier
• 5 V external bias supply
• 3.3 V or 5 V CMOS input logic levels
• Independent high side and low side control inputs
• Logic lockout commands both FETs owhen inputs
are both high at same me
• External resistors to tune SW switching mes
• Robust level shier operaon for hard and so
switching condions
• False trigger immunity from fast switching transients
• Synchronous charging for high-side bootstrap supply
• Low quiescent current mode
• Power-on-reset for low side andand high side power
supplies
• Acve gate pull-down for HS and LS FET allowing for
exible power up sequencing
• Thermally enhanced QFN package with exposed top
for low thermal resistance from juncon to top-side
heatsink
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2024 | | 1
eGaN® FET DATASHEET
EPC23102
Figure 2: EPC23102 Quad Flat No-Lead (QFN)
package (transparent top view)
EPC23102 pinout descripon
Pin
Descripon
1
HSIN
2
LSIN
3
SD
4
VDD
5
VDRV
6
RDRV
7
AGND
8
PGND
9
SW
10
VIN
11
VPHASE
12
RBOOT
13
VBOOT
Pin
Pin Name
Pin Type
Descripon
1
HSIN
L
High side PWM logic input referenced to AGND. Internal pull-down
resistor is connected between HSIN and AGND.
2
LSIN
L
Low side PWM logic input referenced to AGND. Internal pull-down
resistor is connected between LSIN and AGND.
3
SD
L
VDD disable input referenced to AGND. Internal VDD will be disabled
when SD is pulled up to VDRV or external 5 V source. Internal pull-down
resistor is connected between SD and AGND, thereby VDD will follow
VDRV with SD connected to AGND by default.
4
VDD
S
Internal power supply referenced to AGND, connect a bypass capacitor
from VDD to AGND.
5
VDRV
S
External 5 V nominal power supply referenced to AGND, connect a
bypass capacitor from VDRV to AGND.
6
RDRV
G
Insert resistor between RDRV to VDRV to control the turn-on slew rate
of the driven low side FET.
7
AGND
S
Logic ground. Connect bypass capacitors between operang bias
supplies, VDRV and VDD, to AGND. Internal IC connecon between
AGND and PGND. Use star ground external connecon with PGND to
system ground.
8
PGND
P
Input power supply ground return. Connected to source terminal of
internal low side FET. Connect power loop capacitors from VIN to PGND.
9
SW
P
Output switching node. Connected to output of half-bridge power
stage. SW pin connects together the source terminal of high side FET
and the drain terminal of the low side FET.
10
VIN
P
Power bus input. Connected to drain terminal of internal high side FET.
Connect power loop capacitors from VIN to PGND or power source
terminals of low side FET.
11
VPHASE
S
VPHASE is
Kelvin connected to SW, the output switching node.T
Connect an external bootstrap capacitor, Cboot, between VBOOT and
VPHASE.
12
RBOOT
G
Insert resistor between RBOOT and VBOOT to control the turn-on slew
rate of the internal high side FET.
13
VBOOT
S
Floang bootstrap power supply referenced to VPHASE (=SW). Connect
an external bootstrap capacitor, Cboot, between VBOOT and VPHASE.
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2024 | | 2
Pin Type: P = Power, S = Bias Supplies, L = Logic Inputs/Outputs, G = Gate Drive Adjust