eGaN® FET DATASHEET
EPC2302
EPC POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2024 | For more information: info@epc-co.com | 1
General Description
The EPC2302 is a 1.8 mΩ max R
DS(on)
, 100 V eGaN® power transistor in a low inductance 3 x 5 mm QFN
package with exposed top for excellent thermal management. It is tailored to high frequency DC-DC
applications to/from 40 V–60 V and 48 V BLDC motor drives.
The thermal resistance to case top is ~0.2 °C/W, resulting in excellent thermal behavior and easy
cooling. The device features an enhanced PQFN “Thermal-Max” package. The exposed top enhances
top-side thermal management and the side-wettable anks guarantee that the complete side-pad
surface is wetted with solder during the reow soldering process, which protects the copper and
allows soldering to occur on this external ank area for easy optical inspection.
Compared to a Si MOSFET, the footprint of 15 mm
2
is less than half of the size of the best-in-class Si
MOSFET with similar Rds(on) and voltage rating, Q
G
and Q
GD
are signicantly smaller and Q
RR
is 0.
This results in lower switching losses and lower gate driver losses. Moreover, EPC2302 is very fast
and can operate with deadtime less than 10 ns for higher eciency and Q
RR
= 0 is a big advantage
for reliability and EMI. In summary, EPC2302 allows the highest power density due to enhanced
eciency, smaller size, and higher switching frequency for smaller inductor and fewer capacitors.
The EPC2302 enables designers to improve eciency and save space. The excellent thermal behavior
enables easier and lower cost cooling. The ultra-low capacitance and zero reverse recovery of the
eGaN® FET enables ecient operation in many topologies. Performance is further enhanced due to
the small, low inductance footprint.
Application notes:
• Easy-to-use and reliable gate, Gate Drive ON = 5 V typical,
OFF = 0 V (negative voltage not needed)
• Top of FET is electrically connected to source
EPC
2302
XYYWW
XXXX
EPC2302 – Enhancement Mode Power Transistor
V
DS
, 100 V
R
DS(on)
, 1.8 mΩ max
Features
• 100 V
• 1.4 m typical, 1.8 m max R
DS(on)
• 3 x 5 mm QFN package
• Exposed top for top-side thermal management
• Moisture rating MSL2
• Enhanced Thermal-Max package
Applications
• AC-DC chargers, SMPS, adaptors, power supplies
• High Frequency DC-DC Conversion up to 80 V
input (Buck, Boost, Buck-Boost and LLC)
• 24 V–60 V Motor Drives
• High Power Density DC-DC modules from
40 V– 60 V to 5 V–12 V
• Synchronous Rectication
• Solar MPPT
Benets
• Ultra High Eciency
• No Reverse Recovery
• Ultra Low Q
G
• Small Footprint
• Excellent Thermal
EFFICIENT POWER CONVERSION
HAL
Maximum Ratings
PARAMETER VALUE UNIT
V
DS
Drain-to-Source Voltage (Continuous) 100
V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150 °C) 120
I
D
Continuous (T
A
= 25°C) 101
A
Pulsed (25°C, T
PULSE
= 300 µs) 408
V
GS
Gate-to-Source Voltage 6
V
Gate-to-Source Voltage -4
T
J
Operating Temperature –40 to 150
°C
T
STG
Storage Temperature –40 to 150
EPC2302
Package size: 3 x 5 mm
G
D
S
Scan QR code or click
link below for more
information including
reliability reports, device
models, demo boards!
https://l.ead.me/EPC2302
Questions:
EPC GaN Talk
Support Forum
eGaN® FET DATASHEET
EPC2302
EPC POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2024 | For more information: info@epc-co.com | 2
# Dened by design. Not subject to production test.
Static Characteristics (T
J
= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BV
DSS
Drain-to-Source Voltage V
GS
= 0 V, I
D
= 0.15 mA 100 V
I
DSS
Drain-Source Leakage V
DS
= 80 V, V
GS
= 0 V 1 100 μA
I
GSS
Gate-to-Source Forward Leakage V
GS
= 5 V 0.01 4
mAGate-to-Source Forward Leakage
#
V
GS
= 5 V, T
J
= 125°C 0.4 9
Gate-to-Source Reverse Leakage V
GS
= -4 V 0.01 0.2
V
GS(TH)
Gate Threshold Voltage V
DS
= V
GS
, I
D
= 14 mA 0.8 1.3 2.5 V
R
DS(on)
Drain-Source On Resistance V
GS
= 5 V, I
D
= 50 A 1.4 1.8 mΩ
V
SD
Source-to-Drain Forward Voltage I
S
= 0.5 A, V
GS
= 0 V 1.5 V
Thermal Characteristics
PARAMETER TYP UNIT
R
θJC
Thermal Resistance, Junction-to-Case (Case TOP) 0.2
°C/W
R
θJB
Thermal Resistance, Junction-to-Board (Case BOTTOM) 1.5
R
θJA_JEDEC
Thermal Resistance, Junction-to-Ambient (using JEDEC 51-2 PCB) 45
R
θJA_EVB
Thermal Resistance, Junction-to-Ambient (using EPC90142 EVB) 21
Dynamic Characteristics
#
(T
J
= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
C
ISS
Input Capacitance
V
DS
= 50 V, V
GS
= 0 V
3200 4800
pF
C
RSS
Reverse Transfer Capacitance 7
C
OSS
Output Capacitance 1000 1200
C
OSS(ER)
Eective Output Capacitance, Energy Related (Note 1)
V
DS
= 0 to 50 V, V
GS
= 0 V
1300
C
OSS(TR)
Eective Output Capacitance, Time Related (Note 2) 1700
R
G
Gate Resistance 0.5 Ω
Q
G
Total Gate Charge V
DS
= 50 V, V
GS
= 5 V, I
D
= 50 A 23 29
nC
Q
GS
Gate-to-Source Charge
V
DS
= 50 V, I
D
= 50 A
8.9
Q
GD
Gate-to-Drain Charge 2.3
Q
G(TH)
Gate Charge at Threshold 6.3
Q
OSS
Output Charge V
DS
= 50 V, V
GS
= 0 V 85 94
Q
RR
Source-Drain Recovery Charge 0
# Dened by design. Not subject to production test.
Note 1: C
OSS(ER)
is a xed capacitance that gives the same stored energy as C
OSS
while V
DS
is rising from 0 to 50% BV
DSS
.
Note 2: C
OSS(TR)
is a xed capacitance that gives the same charging time as C
OSS
while V
DS
is rising from 0 to 50% BV
DSS
.