FN4545 Rev 0.00 Page 1 of 2
November 1998
FN4545
Rev 0.00
November 1998
ACS32MS
Radiation Hardened Quad 2-Input OR Gate
DATASHEET
The Radiation Hardened ACS32MS is a Quad 2-Input OR
Gate. For each gate, a HIGH level on either A or B input
results in a HIGH level on the Y output. A LOW level on both
the A and B inputs results in a LOW level on the Y output. All
inputs are buffered and the outputs are designed for
balanced propagation delay and transition times.
The ACS32MS is fabricated on a CMOS Silicon on Sapphire
(SOS) process, which provides an immunity to Single Event
Latch-up and the capability of highly reliable performance in
any radiation environment. These devices offer significant
power reduction and faster performance when compared to
ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS32MS are
contained in SMD 5962-98624
.
Features
QML Qualified Per MIL-PRF-38535 Requirements
1.25 Micron Radiation Hardened SOS CMOS
Radiation Environment
- Latch-Up Free Under any Conditions
- Total Dose. . . . . . . . . . . . . . . . . . . . . . .3 x 10
5
RAD (Si)
- SEU Immunity. . . . . . . . . . . . . <1 x 10
-10
Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm
2
)
Input Logic Levels . . . . V
IL
= (0.3)(V
CC
), V
IH
= (0.7)(V
CC
)
Output Current . . . . . . . . . . . . . . . . . . . . . . . . 8mA (Min)
Quiescent Supply Current . . . . . . . . . . . . . . .100A (Max)
Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 12ns (Max)
Applications
High Speed Control Circuits
Sensor Monitoring
Low Power Designs
Ordering Information
ORDERING NUMBER INTERNAL MKT. NUMBER TEMP. RANGE (
o
C) PACKAGE DESIGNATOR
5962F9862401VCC ACS32DMSR-03 -55 to 125 14 Ld SBDIP CDIP2-T14
ACS32D/SAMPLE-03 ACS32D/SAMPLE-03 25 14 Ld SBDIP CDIP2-T14
5962F9862401VXC ACS32KMSR-03 -55 to 125 14 Ld Flatpack CDFP4-F14
ACS32K/SAMPLE-03 ACS32K/SAMPLE-03 25 14 Ld Flatpack CDFP4-F14
5962F9862401V9A ACS32HMSR-03 25 Die N/A
Pinouts
ACS32MS
(SBDIP)
TOP VIEW
ACS32MS
(FLATPACK)
TOP VIEW
A1
B1
Y1
A2
B2
Y2
GND
V
CC
B4
A4
Y4
B3
A3
Y3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1A1
B1
Y1
A2
B2
Y2
GND
V
CC
B4
A4
Y4
B3
A3
Y3
FN4545 Rev 0.00 Page 2 of 2
November 1998
ACS32MS
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Die Characteristics
DIE DIMENSIONS:
Size: 2390mx 2390m (94 mils x 94 mils)
Thickness: 525m 25m (20.6 mils 1 mil)
Bond Pad: 110m x 110m (4.3 x 4.3 mils)
METALLIZATION: AL
Metal 1 Thickness: 0.7m 0.1m
Metal 2 Thickness: 1.0m 0.1m
SUBSTRATE POTENTIAL:
Unbiased Insulator
PASSIVATION
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30m 0.15m
SPECIAL INSTRUCTIONS:
Bond V
CC
First
ADDITIONAL INFORMATION:
Worst Case Current Density: <2.0 x 10
5
A/cm
2
Transistor Count: 116
Metallization Mask Layout
ACS32MS
B1 A1
V
CC
B4
Y1 (3)
A2 (4)
NC
B2 (5)
(12) A4
(11) Y4
NC
(10) B3
(6) (7) (8) (9)
A3Y3GNDY2
(2) (1) (14) (13)