FN3057 Rev 1.00 Page 1 of 11
April 11, 2007
FN3057
Rev 1.00
April 11, 2007
HCS32MS
Radiation Hardened Quad 2-Input OR Gate
DATASHEET
The Intersil HCS32MS is a Radiation Hardened Quad 2-Input
OR Gate. A low on both inputs forces the output to a low state.
The HCS32MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS32MS is supplied in a 14 Ld Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200k RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
• Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day (Typ)
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55°C to +125°C
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
•V
IL
= 30% of V
CC
Max
•V
IH
= 70% of V
CC
Min
• Input Current Levels I
i
5µA @ VOL, VOH
Functional Diagram
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
RANGE (°C) PACKAGE
PKG.
DWG. #
HCS32DMSR Q 5962R95
78101VCC
-55°C to +125°C 14 Ld SBDIP D14.3
HCS32KMSR Q 5962R95
78101VXC
-55°C to +125°C 14 Ld Ceramic
Flatpack
K14.A
HCS32D/
Sample
+25°C 14 Ld SBDIP
HCS32K/
Sample
+25°C 14 Ld Ceramic
Flatpack
HCS32HMSR +25°C Die
Intersil Pb-free hermetic packaged products employ SnAgCu or Au
termination finish, which are RoHS compliant termination finishes and
compatible with both SnPb and Pb-free soldering operations. Ceramic
dual in-line packaged products (CerDIPs) do contain lead (Pb) in the
seal glass and die attach glass materials. However, lead in the glass
materials of electronic components are currently exempted per the
RoHS directive. Therefore, ceramic dual inline packages with Pb-free
termination finish are considered to be RoHS compliant.
TABLE 1. TRUTH TABLE
INPUTS OUTPUTS
An Bn Yn
LLL
LHH
HLH
HHH
NOTE: L = Logic Level Low, H = Logic level High
(1, 4, 9, 12)
An
(2, 5, 10, 13)
Bn
Yn
(3, 6, 8, 11)
