RA6E2 Group

Renesas Microcontrollers

The RA6E2 Group delivers up to 200 MHz of CPU performance using an Arm

Cortex

-M33 core with a code flash memory

ranging from 128 KB to 256 KB, 4 KB of data flash memory, and 40 KB of SRAM. The RA6E2 Group offers a wide set of

peripherals, including USB Full Speed, CANFD, Quad SPI, I3C, and ADC.

Features

R01DS0410EJ0120

Rev.1.20

Jul 7, 2023

■

Arm

Cortex

-M33 Core

●

Armv8-M architecture with the main extension

●

Maximum operating frequency: 200 MHz

●

Arm Memory Protection Unit (Arm MPU)

–

Protected Memory System Architecture (PMSAv8)

–

Secure MPU (MPU_S): 8 regions

–

Non-secure MPU (MPU_NS): 8 regions

●

SysTick timer

–

Embeds two Systick timers: Secure and Non-secure instance

–

Driven by LOCO or system clock

●

CoreSight

™

ETM-M33

■ Memory

●

Up to 256-KB code flash memory

●

4-KB data flash memory (100,000 program/erase (P/E) cycles)

●

40-KB SRAM

■ Connectivity

●

Serial Communications Interface (SCI) × 2

–

Asynchronous interfaces

–

8-bit clock synchronous interface

–

Smart card interface

–

Simple IIC

–

Simple SPI

–

Manchester coding

●

I3C bus interface (I3C)

●

Serial Peripheral Interface (SPI) × 2

●

Quad Serial Peripheral Interface (QSPI)

●

USB 2.0 Full-Speed Module (USBFS)

●

CAN with Flexible Data-rate (CANFD)

●

Serial Sound Interface Enhanced (SSIE)

●

Consumer Electronics Control (CEC)

■ Analog

●

12-bit A/D Converter (ADC12)

●

12-bit D/A Converter (DAC12) × 2

●

Temperature Sensor (TSN)

■ Timers

●

General PWM Timer 16-bit Enhanced (GPT16E) × 6

●

Low Power Asynchronous General Purpose Timer (AGT) × 2

■ Security

●

Arm

TrustZone

–

Up to three regions for the code flash

–

Up to two regions for the data flash

–

Up to three regions for the SRAM

–

Individual secure or non-secure security attribution for each

peripheral

●

128-bit unique ID

●

True Random Number Generator (TRNG)

●

Pin function

–

Secure pin multiplexing

■ System and Power Management

●

Low power modes

●

RealTime Clock (RTC) with calendar

��

Event Link Controller (ELC)

●

Data Transfer Controller (DTC)

●

DMA Controller (DMAC) × 8

●

Power-on reset

●

Low Voltage Detection (LVD) with voltage settings

●

Watchdog Timer (WDT)

●

Independent Watchdog Timer (IWDT)

■ Multiple Clock Sources

●

Main clock oscillator (MOSC) (8 to 24 MHz)

●

Sub-clock oscillator (SOSC) (32.768 kHz)

●

High-speed on-chip oscillator (HOCO) (16/18/20 MHz)

●

Middle-speed on-chip oscillator (MOCO) (8 MHz)

●

Low-speed on-chip oscillator (LOCO) (32.768 kHz)

●

IWDT-dedicated on-chip oscillator (15 kHz)

● Clock trim function for HOCO/MOCO/LOCO

● PLL

●

Clock out support

■ General-Purpose I/O Ports

●

5-V tolerance, open drain, input pull-up, switchable driving ability

■ Operating Voltage

●

VCC: 2.7 to 3.6 V

■ Operating Temperature and Packages

●

Ta = -40℃ to +105℃

–

64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)

–

48-pin QFN (7 mm × 7 mm, 0.5 mm pitch)

–

32-pin QFN (5 mm × 5 mm, 0.5 mm pitch)

●

Ta = -40℃ to +85℃

–

64-pin BGA (5 mm × 5 mm, 0.5 mm pitch)

–

36-pin BGA (4 mm × 4 mm, 0.5 mm pitch)

Datasheet

R01DS0410EJ0120 Rev.1.20

Jul 7, 2023

Page 1 of 92

1. Overview

The MCU integrates multiple series of software- and pin-compatible Arm

-based 32-bit cores that share a common set of

Renesas peripherals to facilitate design scalability and efficient platform-based product development.

The MCU in this series incorporates a high-performance Arm Cortex

-M33 core running up to 200 MHz with the following

features:

●

Up to 256 KB code flash memory

●

40 KB SRAM

●

Quad Serial Peripheral Interface (QSPI)

●

USBFS

●

Analog peripherals

●

Security and safety features

1.1 Function Outline

Table 1.1 Arm core

Feature Functional description

Arm Cortex-M33 core ● Maximum operating frequency: up to 200 MHz

● Arm Cortex-M33 core:

– Armv8-M architecture with security extension

– Revision: r0p4-00rel0

● Arm Memory Protection Unit (Arm MPU)

– Protected Memory System Architecture (PMSAv8)

– Secure MPU (MPU_S): 8 regions

– Non-secure MPU (MPU_NS): 8 regions

● SysTick timer

– Embeds two Systick timers: Secure and Non-secure instance

– Driven by SysTick timer clock (SYSTICCLK) or system clock (ICLK)

● CoreSight

™

ETM-M33

Table 1.2 Memory

Feature Functional description

Code flash memory Maximum 256 KB of code flash memory.

Data flash memory 4 KB of data flash memory.

Option-setting memory The option-setting memory determines the state of the MCU after a reset.

SRAM On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC).

Standby SRAM On-chip SRAM that can retain data in Deep Software Standby mode.

See section x, Standby SRAM.

Table 1.3 System (1 of 2)

Feature Functional description

Operating modes Two operating modes:

● Single-chip mode

● SCI/USB/SWD boot mode

Resets The MCU provides 14 resets.

Low Voltage Detection (LVD) The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The

detection level can be selected by register settings. The LVD module consists of three separate

voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level

input to the VCC pin. LVD registers allow your application to configure detection of VCC changes

at various voltage thresholds.

RA6E2 Datasheet 1. Overview

R01DS0410EJ0120 Rev.1.20

Jul 7, 2023

Page 2 of 92