eGaN® FET DATASHEET
EPC2305
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 1
EPC
2305
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EPC2305 – Enhancement Mode Power Transistor
V
DS
, 150 V
R
DS(on)
, 2.2 mΩ typ
Features
• 150 V
• 2.2 mΩ typical
• 3 x 5 mm QFN Package
Applications
• High frequency DC/DC
• AC/DC Chargers and Adaptors
• BLDC Motor Drive
• eMobility Motor drives
• Solar Optimizer & MPPT
• Synchronous Rectication for chargers, adaptors,
power supplies
• Class D Audio
• Fast charging for phone & notebook, gaming PC
• DC/DC and chargers for eMobility, power tools,
vacuum cleaners
Benets
• Ultra High Eciency
• No Reverse Recovery
• Ultra Low Q
G
• Small Footprint
• Excellent Thermal
EFFICIENT POWER CONVERSION
HAL
Maximum Ratings
PARAMETER VALUE UNIT
V
DS
Drain-to-Source Voltage (Continuous) 150
V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150 °C) 180
I
D
Continuous (T
A
= 25°C) 102
A
Pulsed (25°C, T
PULSE
= 300 µs) 329
V
GS
Gate-to-Source Voltage 6
V
Gate-to-Source Voltage -4
T
J
Operating Temperature –40 to 150
°C
T
STG
Storage Temperature –40 to 150
General Description
The EPC2305 is a 150 V eGaN® power transistor in a low inductance 3 x 5 mm QFN package with
exposed top for excellent thermal management.
The thermal resistance to case top is ~0.2 °C/W, resulting in excellent thermal behavior and easy
cooling. The device features an enhanced PQFN “Thermal-Max” package. The exposed top enhances
top-side thermal management and the side-wettableanks guarantee that the complete side-pad
surface is wetted with solder during the reow soldering process, which protects the copper and
allows soldering to occur on this external ank area for easy optical inspection.
Compared to a Si MOSFET, the footprint of 15 mm
2
is less than half of the size of the best-in-class
Si MOSFET with similar R
DS(on)
and voltage rating, Q
G
and Q
GD
are signicantly smaller and Q
RR
is 0.
This results in lower switching losses and lower gate driver losses. In summary, EPC2305 allows the
highest power density due to enhanced eciency, smaller size, and higher switching frequency for
smaller inductor and fewer capacitors.
The EPC2305 enables designers to improve eciency and save space. The excellent thermal behavior
enables easier and lower cost cooling. The ultra-low capacitance and zero reverse recovery of the
eGaN® FET enables ecient operation in many topologies. Performance is further enhanced due to
the small, low inductance footprint.
G
D
S
Preliminary
EPC2305
Package size: 3 x 5 mm
Scan QR code or click
link below for more
information including
reliability reports, device
models, demo boards!
http s://l.ead.me/EPC2305
Application Notes:
• Easy-to-use and reliable gate, Gate Drive ON = 5 V typical,
OFF = 0 V (negative voltage not needed)
• Top of FET is electrically connected to source
Questions:
eGaN® FET DATASHEET
EPC2305
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 2
# Dened by design. Not subject to production test.
Static Characteristics (T
J
= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BV
DSS
Drain-to-Source Voltage V
GS
= 0 V, I
D
= TBD mA 150 V
I
DSS
Drain-Source Leakage V
DS
= 120 V, V
GS
= 0 V 0.002
mA
I
GSS
Gate-to-Source Forward Leakage V
GS
= 5 V 0.016
Gate-to-Source Forward Leakage
#
V
GS
= 5 V, T
J
= 125°C 0.7
Gate-to-Source Reverse Leakage V
GS
= -4 V 0.006
V
GS(TH)
Gate Threshold Voltage V
DS
= V
GS
, I
D
= 11 mA 0.7 1.1 2.5 V
R
DS(on)
Drain-Source On Resistance V
GS
= 5 V, I
D
= 30 A 2.2 mΩ
V
SD
Source-to-Drain Forward Voltage
#
I
S
= 0.5 A, V
GS
= 0 V 1.4 V
Thermal Characteristics
PARAMETER TYP UNIT
R
θJC
Thermal Resistance, Junction-to-Case (Case TOP) 0.2
°C/W
R
θJB
Thermal Resistance, Junction-to-Board (Case BOTTOM) 1.5
R
θJA_JEDEC
Thermal Resistance, Junction-to-Ambient (using JEDEC 51-2 PCB) 45
R
θJA_EVB
Thermal Resistance, Junction-to-Ambient (using EPC90142 EVB) 21
Dynamic Characteristics
#
(T
J
= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
C
ISS
Input Capacitance
V
DS
= 75 V, V
GS
= 0 V
2900
pF
C
RSS
Reverse Transfer Capacitance 7
C
OSS
Output Capacitance 920
C
OSS(ER)
Eective Output Capacitance, Energy Related (Note 1)
V
DS
= 0 to 75 V, V
GS
= 0 V
1100
C
OSS(TR)
Eective Output Capacitance, Time Related (Note 2) 1400
R
G
Gate Resistance 0.5 Ω
Q
G
Total Gate Charge V
DS
= 75 V, V
GS
= 5 V, I
D
= 30 A 21
nC
Q
GS
Gate-to-Source Charge
V
DS
= 75 V, I
D
= 30 A
6.3
Q
GD
Gate-to-Drain Charge 2.6
Q
G(TH)
Gate Charge at Threshold 4.4
Q
OSS
Output Charge V
DS
= 75 V, V
GS
= 0 V 105
Q
RR
Source-Drain Recovery Charge 0
# Dened by design. Not subject to production test.
All measurements were done with substrate shorted to source.
Note 1: C
OSS(ER)
is a xed capacitance that gives the same stored energy as C
OSS
while V
DS
is rising from 0 to 50% BV
DSS
.
Note 2: C
OSS(TR)
is a xed capacitance that gives the same charging time as C
OSS
while V
DS
is rising from 0 to 50% BV
DSS
.