QUICK START GUIDE
EPC90151
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | | 2
DESCRIPTION
The EPC90151 development board is a 100 V maximum device voltage,
15|A maximum output current, half bridge featuring the EPC23103
Integrated ePower™ Stage. The purpose of this development board is
to simplify the evaluation process of the EPC23103 by including all the
critical components on a single board that can be easily connected into
the majority of existing converter topologies.
The EPC90151 development board measures 2” x 2” and contains one
EPC23103 integrated ePower™ Stage in a half bridge conguration.
The board also contains all critical components and the layout supports
optimal switching performance. There are also various probe points to
facilitate simple waveform measurement and eciency calculation.
A block diagram of the circuit is given in gure 1.
For more information on the IC associated with this board, please refer
to its datasheets available on EPC’s website: EPC23103 datasheet.
The datasheet should be read in conjunction with this quick start guide.
Table 1: Performance Summary (T
A
= 25°C) EPC90151
Symbol Parameter Conditions Min Nominal Max Units
V
DD
Gate Drive Input
Supply Range
7.5 12 V
V
IN
Bus Input Voltage
Range
(1)
10 80 V
I
OUT
Switch Node Output
Current
(2)
15 A
V
PWM
PWM Logic Input
Voltage Threshold
(3)
Input ‘High’
Input ‘Low’
3.5
0
5.5
1.5
V
V
Minimum ‘High’ State
Input Pulse Width
V
PWM
rise and
fall time < 10ns
50 ns
Minimum ‘Low’ State
Input Pulse Width
(4)
V
PWM
rise and
fall time < 10ns
200 ns
(1) Maximum input voltage depends on inductive loading, maximum switch node ringing
must be kept under 100 V for EPC23103.
(2) Maximum current depends on die temperature – actual maximum current is aected by
switching frequency, bus voltage and thermal cooling.
(3) When using the on board logic buers, refer to the EPC23103 datasheet when bypass-
ing the logic buers.
(4) Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
Figure 1: Block diagram of EPC90151 development board
Delay
match
level
shift
150 k
Logic
+
UVLO
+
XLO
Level
shift
Output
driver
Enable
logic
V
Cntl
EN
L
1
LS
IN
HS
IN
V
Drv
V
Drv
R
nEV
V
DD
PWM
GND
C
IN
C
OUT
V
IN
PGND
SW
Phase
GND
GND
V
DD
V
IN
V
IN
V
Boot
R
Boot
R
Boot
R
DRV
R
DRV
Sync
boot
C
Boot
C
VDD
C
Drv
GND
Switch node
DC output
Logic and
dead-time
adjust
Output
driver
EN
Logic
supply
U
1
V
DD
EPC23103
EPC90151 development board
Back viewFront view