RX671 Group
Renesas MCUs
Datasheet
R01DS0373EJ0110 Rev.1.10 Page 1 of 178
Apr 15, 2022
Features
■ 32-bit RXv3 CPU core
•
Maximum operating frequency: 120 MH z
Capable of 707 CoreMark in o peration at 120 MHz
•
Double-precision 64-bit IEEE-754 floating point
•
A collective register bank save function is available.
•
Supports the mem ory protection unit (MPU)
•
JTAG and FINE (one-line) debugging interfaces
■ Low-power design and architecture
•
Operation from a sing le 2.7- to 3.6-V supply
•
Battery supply of backup power allows continued operations of the
RTC and the backup registers.
•
Four low-power mode s
■ On-chip code flash memory
•
Supports versions with up to 2 Mbytes of ROM
•
No wait cycles at up to 60 MHz or when the ROM cache is hit, one-
wait state at up to 120 MHz
•
User code is programmable by on-board or off-board programming.
•
Programming/erasing a s background operations (BG Os)
•
A dual-bank structure allows exchanging the start-up bank.
■ On-chip data flash memory
•
8 Kbytes, reprogramm a ble up to 100,000 times
•
Programming/erasing a s background operations (BG Os)
■ On-chip SRAM
•
384 Kbytes of SRAM (no wait states)
•
4 Kbytes of standby R AM (backup on deep software standby)
■ External address space
•
Buses for full-speed data transfer (maximum operating frequency of
60 MHz)
•
8 CS areas
•
8- or 16-bit bus space is selectable per area
•
Independent SDRA M area (128 Mby tes)
■ Data transfer
•
DMACAb: 8 channels
•
DTCb: 1 ch ann el
•
EXDM ACa: 2 channels
■ Reset and supply management
•
Power-on reset (POR)
•
Low voltage detection (LV D) with voltage settings
•
Backup dom ain low power detection
■ Clock functions
•
External crys tal reson ator or internal PLL for operation at 8 to 24
MHz
•
A sub-clock oscillator connectable to a 32.768-kHz cry stal resonator
•
Internal 240-kHz LOC O and HOCO selectable from 16, 18, and 20
MHz
•
120-kHz clock for the IWDTa
■ Real-time clock
•
Adjustment functions (30 seconds, leap year, and error)
•
Real-time clock counting and binary counting modes are selectable
•
Time capture in response to an event-signal input
■ Independent watchdog timer
•
Operates with the 120-kHz clock frequency generated by the
dedicated low-speed oscillator
■ Useful functions for IEC60730 compliance
•
Oscillation-stoppage detection, frequency measurement, CRCA,
IWDTa, self-diagnostic function fo r the A/D converter, etc.
•
Register write protection function that protects imp ortan t registers
against overwriting
■ Remote control signal receiver
■ Various communications interfaces
•
PHY layer (up to 2 channels) for host/function or OTG controller
(1 channel) with full-speed USB 2.0 transfer
•
CAN (com pliant w ith ISO 11898-1), incorporating 32 mailbox es (u p
to 2 channels)
•
SCIk and SCIh with multiple functionalities (up to 13 channels)
Choose from among asynchronous mo de, clock -synchro nou s mod e,
smart-card interface mode, simplified SPI, simplified I
2
C, and
extended serial mode.
•
SCIm with 16-byte transmission and reception FIFOs (up to 2
channels)
•
Up to two RSCIs with Manchester encoding and HBS functionality
•
The I
2
C bus interfaces RIIC and RIIC HS for transfer at up to 3.4
Mbps (up to 3 channels), and the RIICHS also supports high-speed
mode.
•
Single I/O RSPId (3 channels), single I/O R SPIA (1 channel), and
quad QSPIX (1 cha nnel). The QSPIX supp orts fetching fro m serial
flash memory.
•
SD host interface (1 channel) with a 1- or 4-bit SD bus for use with
SD memory or SDIO
•
Serial sound interface supporting various audio data formats,
including I
2
S
■ Up to 25 extended-function timers
•
16-bit TPUa, MTU3a
•
8-bit TMRb (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2
channels)
■ 12-bit A/D converter
•
Two 12-bit units (8 chann els for unit 0; 12 c ha nnels for unit 1)
•
Self diagnosis, detection of analog input disconnection
■ Temperature sensor for measuring temperature
within the chip
■ Capacitive touch sensing unit
•
Self-capacitance method: A single pin configures a sing le key,
supporting up to 17 keys
•
Mutual capacitance method: Matrix configuration with 17 pins,
supporting up to 64 keys
■ Encryption function
•
Trusted Secure IP (TSIP)
AES128/192/256, TDES, ARC4, RSA, ECC,
True-random number generator (TRNG), SHA1, SHA224, SHA256,
MD5, GHASH, Prevention of the illicit copying of keys
■ Up to 114 pins for general I/O ports
•
5-V tolerance, open drain, input pull-up, switchable driving ab ility
■ Operating temp. range
•
D-version: –40
°
C to +85
°
C
•
G-version: –40
°
C to +105
°
C
PLQP0144KA-B 20 × 20 mm, 0.50-mm pitch
PLQP0100KB-B 14 × 14 mm, 0.50-mm pitch
PLQP0064KB-C 10 × 10 mm, 0.50-mm pitch
PTLG0145JC-A 9 × 9 mm, 0.65-mm pitch
PTLG0145KB-A 7 × 7 mm, 0.50-mm pitch
PTLG0100JB-A 7 × 7 mm, 0.65-mm pitch
PTBG0064KB-A 4.5 × 4. 5 mm, 0.50-mm pitch
PWQN0048KC -A 7 × 7 mm, 0.50- m m pit ch
120-MHz 32-bit RX MCU, on-chip double-precision FPU, 707 CoreMark,
up to 2-MB flash memory (supporting the dual bank function), 384-KB SRAM,
various communications interfaces, including SD host interface, Quad SPI, and CAN, Capacitive touch sensing unit,
12-bit A/D converter, RTC, Encryption function, Serial sound interface, Remote control signal receiver
R01DS0373EJ0110
Rev.1.10
Apr 15, 2022
Features
RX671 Group 1. Overview
R01DS0373EJ0110 Rev.1.10 Page 2 of 178
Apr 15, 2022
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 give a comparison of the functions of products in different
packages.
Table 1.1 is an outline of maximum specifications, and the peripheral mod ules and the number of channels of the
modules differ depending on the number of pins on the package. For details, see Table 1.2, Comparison of Functions
for Different Packages.
Table 1.1 Outline of Specifications (1/10)
Classification Module/Function Description
CPU CPU • Maximum operating frequency: 120 MHz
• 32-bit RX CPU (RXv3)
• Minimum instruction execution time: One instruction per state (cycle of the system
clock)
• Address space: 4-Gbyte linear
• Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Ten 32-bit registers
Accumulator: Two 72-bit registers
• 113 instructions
Instructions installed as standard: 111
Basic instructions: 77
Single-precision floating-point operation instructions: 11
DSP instructions: 23
Instructions for register bank save function: 2
• Addressing modes: 11
• Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
• On-chip 32-bit multiplier: 32 × 32 → 64 bits
• On-chip divider: 32 / 32 → 32 bits
• Barrel shifter: 32 bits
FPU • Single precision (32-bit) floating point
• Data types and floating-point exceptions in conformance with the IEEE754 standard
Double-precision
floating point
coprocessor
• Double-precision floating-point register set
Double-precision floating-point data registers: 16, each with 64-bit width
Double-precision floating-point control registers: Four, each with 32-bit width
• Double-precision floating-point processing instructions: 21
• Notifying the interrupt controller of double-precision floating-point exceptions
Register bank save
function
• Fast collective saving and restoration of the values of CPU registers
• 16 save register banks
Memory Code flash memory • Capacity: 1 Mbyte/1.5 Mbytes/2 Mbytes
• ROM cache: 8 Kbytes
• 60 MHz ≤ No-wait cycle access
120 MHz ≤ 1-wait cycle access
• Instructions hitting the ROM cache or operand = 120 MHz: No-wait access
• On-board programming: Four types
• Off-board programming (parallel programmer mode)
• Instructions are executable only for the program stored in the TM target area by using
the Trusted Memory (TM) function and protection against data reading is realized.
• A dual-bank structure allows programming during reading or exchanging the start-up
areas
Data flash memory • Capacity: 8 Kbytes
• Programming/erasing: 100,000 times
Unique ID
• 16-
byte unique ID for the device
RAM • Capacity: 384 Kbytes
• 120 MHz, no-wait access
Standby RAM • Capacity: 4 Kbytes
• Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access