APPLICATION NOTE: AN010
GaN FETs and ICs Visual Guide
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2023 | | 1
Enhancement Mode GaN FETs and ICs
Visual Characterization Guide
A detailed description of the EPC enhance-
ment mode transistors and integrated
circuits physical characteristics is given
including the visual criteria all devices
must meet before they are released for
shipment to customers. This article, used
in conjunction with the two companion
articles, “Assembling eGaN FETs”
1
, and
“EPC GaN Transistor Parametric Char-
acterization Guide”
2
, gives the user a
set of tools to develop circuits and sys-
tems that take advantage of the en-
hancement mode GaN FET’s and IC’s
advanced form factor and consequent
unprecedented performance potential.
EFFICIENT POWER CONVERSION
OVERVIEW OF GALLIUM NITRIDE
(GaN) TECHNOLOGY
In June of 2009, Ecient Power Conversion
Corporation (EPC) introduced the rst en-
hancement mode gallium nitride on silicon
power transistors designed specically as
power MOSFET replacements. These prod-
ucts were developed to be produced in high
volume at low cost using standard silicon
manufacturing technology and facilities.
For more information about EPC’s GaN tech-
nology, go to www.epc-co.com.
STRUCTURE
A device’s cost eectiveness starts with
leveraging existing production infrastructure.
EPC’s process begins with silicon wafers. A
thin layer of Aluminum Nitride (AlN) is grown
on the Silicon to isolate the device structure
from the substrate. On top of this AlN, a thick
layer of highly resistive GaN is grown. This
layer provides a foundation on which to build
the active transistor. An electron generating
material comprised of Aluminum, Gallium,
and Nitrogen (AlGaN) is applied on top of the
GaN. This layer creates an abundance of free
electrons just below it. Further processing
forms a depletion region under the gate. To
enhance the transistor, a positive voltage
is applied to the gate in a similar manner
to turning on an n-channel, enhancement
mode power MOSFET. A cross section of this
structure, repeated many times to form a
complete power device, is depicted in gure
1. The end result is a fundamentally simple,
cost eective solution for power switching
3
.
EPC’s GaN transistors are lateral devices with
all three terminals: gate, drain, and source, on
the top side of the chip. Generally, EPC devices
have three layers of metal used to connect the
active device to the outside world (g 2). The
top metal layer is then used as a foundation
for solder bumps as shown in Figure 3. This
conguration allows EPC’s GaN transistors to
eliminate unnecessary elements of traditional
power MOSFET packaging that contribute
to higher inductance, thermal and electrical
resistance, higher costs, and compromised
reliability.
Alana Nakata, Vice President, Product Engineering, Efficient Power Conversion Corporation
Si
S G D
GaN
Electron generating layer
Dielectric
Aluminum nitride
isolation layer
G
D
S
Figure 1: EPC’s GaN transistor structure
Silicon
Active GaN device region
Solder bumps
Copper traces
Printed circuit board
Aluminum Nitride
Figure 3: Flip chip
SILICON SUBSTRATE
G
S
D
Semi insulating GaN (uGaN)
Interlayer insulation
Interlayer insulation
Top layer insulation
Metal layer 3
Metal layer 2
Metal layer 1
AIGaN
strain
layer
AIN
isolation
layer
Figure 2: Device construction
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GaN FETs and ICs Visual Guide
A VISUAL TOUR
This section includes bump and side views of selected EPC’s GaN transistors and integrated circuits. Solder bars or solder balls are used to make reliable
connections directly to a printed circuit board. A polyimide coating on top of multiple silicon dioxide and silicon nitride layers are used to seal the active
device from the outside environment.
This section shows a selection of EPC’s eGaN FETs and ICs. For a full listing of products please see the website at: epc-co.com/epc/Products/eGaNFETsandICs
(Downloadable PDF: Click on the part number to be taken to its details page and access to its datasheet on EPC’s website.)
EPC2040
0.85 mm x 1.2 mm
Max size (µm):
880 x 1230
2.1 mm x 1.6 mm
Max size (µm):
2136 x 1662
EPC2051
1.3 mm x 0.85 mm
Max die size (µm):
1330 x 880
685 +/- 25
35
Solder
65 Cu
B
A
c
e
c c
d
f
2
1
4
3
6
5
1
c
B
e
d
c
c
f
41
2
5
3
6
(625)
Seating Plane
815 Max
165+/- 17
A
Pad 1 is Gate;
Pads 2, 5 are Drain;
Pads 3, 4, 6 are Source
EPC2214
1.35 mm x 1.35 mm
Max die size (µm):
1380 x 1380
B
A
d
c c
d
d c c
805
685 +/−15120 +/
−12
Seating Plane
3 9
2 8
1 7
6
5
4
B
A
i
1 2
3
4
5
6
j
g
x2
e
e
d
f
h
C
i
X2
EPC8002
EPC8004
EPC8009
EPC8010
EPC2202
EPC2212
EPC2016C
2.05 mm x 0.85 mm
Max die size (µm):
2080 x 880
815 Max
100 +/- 20
Seating Plane
(685)
B
A
d
X2
c
e
g
3 4 5 6
g
X3
f
f
2
1
X4
815 Max
100 +/- 20
Seating Plane
(685)