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EFM32PG22 Errata
This document contains information on the EFM32PG22 errata. The latest available revision of this device is revision C.
Errata that have been resolved remain documented and can be referenced for previous revisions of this device.
The device data sheet explains how to identify the chip revision, either from the package marking or electronically.
Errata effective date: December, 2022.
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1. Errata Summary
The table below lists all known errata for the EFM32PG22 and all unresolved errata of the EFM32PG22.
Table 1.1. Errata Overview
Designator Title/Problem Workaround
Exists
Exists on
Revision:
C
CUR_E302 Extra EM1 Current if FPU is Disabled Yes X
DCDC_E302 DCDC Interrupts Block EM2/3 Entry or Cause Unexpected Wake-up Yes X
EMU_E303 Watchdog Reset Hangs System Entering EM2 or EM3 Yes X
EUART_E301 EUART Receiver Enters Lockup State when Using Low Frequency IrDA
Mode
Yes X
EUART_E302 Incorrect Stop Bits Lock Receiver Yes X
I2C_E303 I2C Fails to Indicate New Incoming Data Yes X
IADC_E306 Changing Gain During a Scan Sequence Causes an Erroneous IADC
Result
Yes X
TIMER_E301 Continuous Overflow and Underflow Interrupts in Quadrature Counting
Mode
Yes X
USART_E301 Possible Data Transmission on Wrong Edge in Synchronous Mode Yes X
USART_E302 Additional SCLK Pulses Can Be Generated in USART Synchronous
Mode
Yes X
USART_E304 PRS Transmit Unavailable in Synchronous Secondary Mode No X
EFM32PG22 Errata
Errata Summary
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