Revision History
16Gb DDR4 AS4C1G16D4 - 96 ball FBGA PACKAGE
Revision Details Date
Rev 1.0 Initial Release October 2022
AS4C1G16D4
Confidential
-1／365-
Rev.1.0 October 2022
Features
•V
DD
= V
DDQ
= 1.2V ±60mV
•V
PP
= 2.5V, –125mV, +250mV
•On-die, internal, adjustable V
REFDQ
generation
•1.2V pseudo open-drain I/O
•Refresh time of 8192-cycle at T
C
temperature range:
– 64ms, at –40°C to 85°C
– 32ms, at >85°C to 95°C
•8 internal banks (x16): 2 groups of 4 banks each
•8n-bit prefetch architecture
•Programmable data strobe preambles
•Data strobe preamble training
•Command/Address latency (CAL)
•Multipurpose register READ and WRITE capability
•Write leveling
•Self refresh mode
•Low-power auto self refresh (LPASR)
•Temperature controlled refresh (TCR)
•Fine granularity refresh
•Self refresh abort
•Maximum power saving
•Output driver calibration
•Nominal, park, and dynamic on-die termination
(ODT)
•Data bus inversion (DBI) for data bus
•Command/Address (CA) parity
•Databus write cyclic redundancy check (CRC)
•Per-DRAM addressability
•Connectivity test
•JEDEC JESD-79-4 compliant
•sPPR and hPPR capability
Options
1
Marking
1G16
• Configuration
– 1 Gig x 16
• 96-ball FBGA package (Pb-free) – x16
– 9mm x 13mm
• Timing – cycle time
•
– 0.625ns @ CL = 22 (DDR4-3200)
-062
Operating temperature
– Commercial (0° ≤
T
C
≤
95°C)
Table 1: Key Timing Parameters
Speed Grade
1
Data Rate (MT/s) Target CL-nRCD-nRP
t
AA (ns)
t
RCD (ns)
t
RP (ns)
-062
3200 22-22-22 13.75 13.75 13.75
Note:
1. Refer to the Speed Bin Tables for additional details.
Ordering Information
1600
96-ball FBGA
Commercial 0°C to 95°C
1G x 16
AS4C1G16D4-062BCN
Product part No
Org Temperature Tc
Max Clock (MHz)
Package
AS4C1G16D4
Confidential
-2／365-
Rev.1.0 October 2022