QUALIFICATION REPORT
EPC Reliability & Quality
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 1
EPC eGaN® FET
Qualication Report
EPC2302
EFFICIENT POWER CONVERSION
This report summarizes the Product Qualication results for EPC
part number EPC2302 which meets all required qualication
requirements and is released for production.
Qualication Test Overview
EPC’s eGaN FETs were subjected to a wide variety of stress tests under
conditions that are typical for silicon-based power MOSFETs. These
tests included:
– High temperature reverse bias (HTRB): Parts are subjected to a drain-
source voltage at the maximum rated temperature
– High temperature gate bias (HTGB): Parts are subjected to a gate-
source voltage at the maximum rated temperature
– High temperature storage (HTS): Parts are subjected to heat at the
maximum rated temperature
– Temperature cycling (TC): Parts are subjected to alternating high-
and low temperature extremes
– High temperature high humidity reverse bias (H3TRB): Parts are
subjected to humidity under high temperature with a drain-source
voltage applied
– Moisture sensitivity level (MSL): Parts are subjected to moisture,
temperature, and three cycles of reow
– Unbiased highly accelerated stress test (uHAST): Parts are subjected
to extreme temperature and humidity for a length of time.
– Electrostatic Discharge (ESD) Characterization: Parts are tested
under both Human Body Model (HBM) and Charged Device Model
(CDM) to assess device susceptibility to electrostatic discharge
events.
The stability of the devices is veried with DC electrical tests after stress
biasing. The electrical parameters are measured at time-zero and at
interim readout points at room temperature. Electrical parameters such
as the gate-source leakage, drain-source leakage, gate-source threshold
voltage, and on-state resistance are compared against the data sheet
specications. A failure is recorded when a part exceeds the datasheet
specications. eGaN FETs are stressed to meet the latest Joint Electron
Device Engineering Council (JEDEC) standards when possible.
Parts for all tests except for TC were mounted onto high Tg FR4 adaptor
cards. Adaptor cards of 1.6 mm in thickness with two copper layers were
used. The top copper layer was 1 oz. or 2 oz., and the bottom copper
layer was 1 oz. Kester NXG1 type 3 SAC305 solder with no clean ux was
used for mounting the parts onto an adaptor card.
Scope
The testing matrix in this qualication report covers the qualica-
tion of EPC2302, a 100 V eGaN power transistor in a QFN package
with exposed top.
Part Number
Voltage
(V)
Max R
DS(on)
(mΩ)
Package Size
(mm x mm)
EPC2302 100 1.8 3 x 5
Dr. Shengke Zhang, VP of Reliability, Efficient Power Conversion Corporation