eGaN® FET DATASHEET
EPC2055
EPCPOWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 1
EFFICIENT POWER CONVERSION
HAL
EPC2055 – Enhancement Mode Power Transistor
V
DS
, 40 V
R
DS(on)
, 3.6 mΩ
I
D
, 29 A
Maximum Ratings
PARAMETER VALUE UNIT
V
DS
Drain-to-Source Voltage (Continuous)
40
V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150 °C)
48
I
D
Continuous (T
A
= 25°C)
29
A
Pulsed (25°C, T
PULSE
= 300 µs)
161
V
GS
Gate-to-Source Voltage
6
V
Gate-to-Source Voltage
-4
T
J
Operating Temperature
-40 to 150
°C
T
STG
Storage Temperature
-40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
R
θJC
Thermal Resistance, Junction-to-Case 1
°C/W R
θJB
Thermal Resistance, Junction-to-Board 2.5
R
θJA
Thermal Resistance, Junction-to-Ambient (Note 1) 64
Note 1: R
θJA
is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
# Dened by design. Not subject to production test.
Static Characteristics (T
J
= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BV
DSS
Drain-to-Source Voltage V
GS
= 0 V, I
D
= 0.5 mA 40 V
I
DSS
Drain-Source Leakage V
GS
= 0 V, V
DS
= 32 V 0.01 0.4
mA
I
GSS
Gate-to-Source Forward Leakage V
GS
= 5 V 0.01 1.6
Gate-to-Source Forward Leakage
#
V
GS
= 5 V, T
J
= 125°C 0.1 5
Gate-to-Source Reverse Leakage V
GS
= -4 V 0.01 0.4
V
GS(TH)
Gate Threshold Voltage V
DS
= V
GS
, I
D
= 7 mA 0.7 1.1 2.5 V
R
DS(on)
Drain-Source On Resistance V
GS
= 5 V, I
D
= 15 A 3 3.6 mΩ
V
SD
Source-Drain Forward Voltage
#
I
S
= 0.5 A, V
GS
= 0 V 1.9 V
Gallium Nitride’s exceptionally high electron mobility and low temperature coecient allows
very low R
DS(on)
, while its lateral device structure and majority carrier diode provide exceptionally
low Q
G
and zero Q
RR
. The end result is a device that can handle tasks where very high switching
frequency, and low on-time are benecial as well as those where on-state losses dominate.
EPC2055 eGaN® FETs are supplied only in
passivated die form with solder bars.
Die Size: 2.5 mm x 1.5 mm
Applications
• DC-DC Converters
• Isolated DC-DC
Converters
• Sync rectication
• High frequency (2 MHz)
Ultra-thin Point of Load
Converters with Input
12 V – 24 V
• Lidar
• USB-C Battery Chargers
• LED Lighting
• 12 V – 24 V Input Motor
Drivers
Benets
• Ultra High Eciency
• No Reverse Recovery
• Ultra Low Q
G
• Small Footprint
G
D
S
eGaN® FET DATASHEET
EPC2055
EPCPOWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 2
160
140
120
100
80
60
40
20
0
0 0.5 1.0 1.5 2.0 2.5 3.0
I
D
– Drain Current (A)
Figure 1: Typical Output Characteristics at 25°C
V
DS
– Drain-to-Source Voltage (V)
V
GS
= 5 V
V
GS
= 4 V
V
GS
= 3 V
V
GS
= 2 V
I
D
– Drain Current (A)
V
GS
– Gate-to-Source Voltage (V)
1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 2: Typical Transfer Characteristics
25˚C
125˚C
V
DS
= 3 V
25˚C
125˚C
V
DS
= 3 V
160
140
120
100
80
60
40
20
0
12
10
8
6
4
2
0
2.5 3.02.0 3.5 4.0 4.5 5.0
R
DS(on)
– Drain-to-Source Resistance (mΩ)
V
GS
– Gate-to-Source Voltage (V)
Figure 3: R
DS(on)
vs. V
GS
for Various Drain Currents
I
D
= 7 A
I
D
= 15 A
I
D
= 22 A
I
D
= 30 A
2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 4: Typical R
DS(on)
vs. V
GS
for Various Temperatures
R
DS(on)
– Drain-to-Source Resistance (mΩ)
V
GS
– Gate-to-Source Voltage (V)
25˚C
125˚C
V
DS
= 3 V
25˚C
125˚C
I
D
= 15 A
12
10
8
6
4
2
0
Dynamic Characteristics
#
(T
J
= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
C
ISS
Input Capacitance
V
DS
= 20 V, V
GS
= 0 V
841 1111
pF
C
RSS
Reverse Transfer Capacitance
8.8
C
OSS
Output Capacitance
408 612
C
OSS(ER)
Eective Output Capacitance, Energy Related (Note 2)
V
DS
= 0 to 20 V, V
GS
= 0 V
574
C
OSS(TR)
Eective Output Capacitance, Time Related (Note 3)
668
R
G
Gate Resistance
0.4 Ω
Q
G
Total Gate Charge
V
DS
= 20 V, V
GS
= 5 V, I
D
= 15 A 6.6 8.5
nC
Q
GS
Gate-to-Source Charge
V
DS
= 20 V, I
D
= 15 A
2.3
Q
GD
Gate-to-Drain Charge
0.7
Q
G(TH)
Gate Charge at Threshold
1.6
Q
OSS
Output Charge
V
DS
= 20 V, V
GS
= 0 V 13 20
Q
RR
Source-Drain Recovery Charge
0
# Dened by design. Not subject to production test.
All measurements were done with substrate connected to source.
Note 2: C
OSS(ER)
is a xed capacitance that gives the same stored energy as C
OSS
while V
DS
is rising from 0 to 50% BV
DSS
.
Note 3: C
OSS(TR)
is a xed capacitance that gives the same charging time as C
OSS
while V
DS
is rising from 0 to 50% BV
DSS
.