1. Errata Summary
Table 1.1. Errata History Overview
Designator Title/Problem Exists on Revision:
B C
ADC_E202 Wait After POR or EM4S Wakeup X X
ADC_E206 PROGERRIF (Program Error Interrupt Flag) Will Not Clear X X
ADC_E207 ADC Scan Repeat Mode with APORT X X
ADC_E208 ADC Interrupt Flags X X
ADC_E209 ADC and PRS Triggers X X
ADC_E210 ADC with PRS and Software Triggers X X
ADC_E211 ADC Single Repeat Mode and Tailgating X X
ADC_E212 ADC with PRS in ASYNC Mode X X
ADC_E213 ADC KEEPINSLOWACC Mode X X
ADC_E214 Using ADC CHCONMODE with PRS X X
ADC_E215 ADC CHCONMODE Set to MAXRESP Causes Extra Latency X X
ADC_E216 ADC Conversion Start Delay X X
ADC_E217 Multiple CLK Mode Switches X X
ADC_E218 SINGLEACT and SCANACT Status Flags Delayed X X
ADC_E219 STOP Command Causing FIFO Corruption X X
ADC_E220 AUXHFRCO in ASYNC mode with ASYNC CLK in ASNEEDED
mode
X X
ADC_E221 ADC Temperature Sensor Must be Used in LOWACC Mode X X
ADC_E222 ADC EM2 Wakeup on a Comparator Match Disables EM2 En-
try
X X
ADC_E223 Delayed ADC Conversion or Warmup Start X X
CORE_E201 SYSTICK and an External Clock X X
CRYPTO_E201 Full CRYPTO Not Available in All Value Devices — X
CUR_E201 EM2 and EM3 Current Consumption X X
CUR_E202 EM2/3 Current Consumption at Cold Temperatures X —
DBG_E201 AUXHFRCO Debug Limitations X X
DBG_E202 Debug Access to ADC and LEUART not Functioning as Inten-
ded
X X
DCDC_E201 DCDC Stops Regulating During a Fast EM0/1 to EM2/3/4H
Transition
X —
DCDC_E202 Regulated DCDC Output Can Dip on EM2 Entry X X
DCDC_E203 Regulated DCDC Output Can Dip on EM2 Entry if not in LN
Mode
X X
EFR_E201 Bit Access Not Supported for Low Energy Peripherals X X
EFR_E202 Read-Clear Access for LETIMER0 and RTCC Interrupts X X
EFR32FG1 Errata History
Errata Summary
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