AF204
Arbitrary Broadband Signal Generation
L and S bands
Automatic Test Equipment (ATE)
FMC HPC
Single
12 bit 3 Gsps DAC
Conduction or Air
-Cooled
High Speed Data Conversion
& Signal Processing Solutions
AF204
Applications
· Test and Measurement
· Radar Transmitter
· Software Defined Radio
Features
· 1 channel 12-bit, 3 Gsps DAC
· External clock and reference input
· Internal low jitter clock generation
· External trigger input and output
· VITA 57 FMC form factor
· Air cooled
and Conduction cooled rugged
versions
· FPGA firmware cores
· Windows® and Linux® drivers
Overview
The AF204 is part of ApisSys' range of modular IOs solutions based on the VITA 57, FPGA
Mezzanine Card standard.
The AF204 provides customers with a single channel 12-bit up to 3 Gsps DAC capability, ideally
suited for test and measurement, Software Defined Radio or Radar Transmitter applications.
The AF204 DAC channel is AC coupled with an output bandwidth wider than 5 GHz for a full scale
signal of -2 dBm (500 mVpp).
The AF204 provides an internal ultra low jitter clock generation and can be used with either an
external clock or an external reference for higher flexibility.
The AF204 features an external trigger input and an external trigger output used to synchronize
processing with external events.
The AF204 is fully supported on ApisSys 3U VPX FPGA processing engines, making it ideally suited
for test and measurement, Software Defined Radio or Ultra Wideband Radar Transmitters
applications.
12-bit 3 Gsps Digital-Analog Converter
The AF204 Digital to Analog
conversion is
performed by one e2v EV12DS130 12-bit
3
Gsps DAC.
The AF204 provides one front panel SSMC
connector for the analog output.
The output signal is s
ingle ended AC coupled
with an output bandwidth from 1
MHz to more
than 5 GHz with -2 dBm output level.
Clock
The AF204
provides an internal ultra low jitter
clock generator locked on a 100 MHz internal
reference.
The AF204 provides a front panel SSMC
connector for an external reference from
10 to
100 MHz, a front panel SSMC
connector for an
external clock input from 500 MHz to 3 GHz
and
a front panel SSMC connector
for an external
clock output.
Estimated jitter from the internal clock
generation (i
ncluding 100 MHz reference and
clock distribution) is below 200 fs for a 3
GHz
clock. Added jitter on external clock is lower
than 100 fs.
Trigger and Synchronization
The AF204 provides a front panel SSMC
connector for an external trigger input
and one
front panel SSMC connector for an external
trigger output.
The trigger input and output signals
are buffered
with ultrafast PECL buffers.
FMC interface
The AF204 features a VITA 57 –
FMC (FPGA
Mezzanine Card) compliant slot.
The FMC uses High Pin Count (HPC) interface
with 1.8V or 2.5V Vadj.
The FMC MGT interfaces are unused.
Firmware
The AF204
comes with a firmware package
which includes VHDL cores allowing control and
communication with all AF204
hardware
resources.
A base design is provided which demonstrates
the use of the AF204 and
gives users a starting
point for firmware development.
The AF204
firmware package is supported on
the Xilinx ISE
®
14
design suite and later versions.
The AF204
firmware package has been fully
vali
dated on AV103 and other ApisSys FMC
carrier products.
Software
The AF204
is delivered with control software for
Windows XP and 7, and Linux, compatible with
AV103 and other ApisSys FMC carrier products.
An application exampl
e is provided as source
code.
Ruggedization
The AF204
is delivered in air cooled and
conduction cooled standard or rugged versions
for use in severe environmental conditions.
Standard VITA 47 supported ruggedization
levels are EAC4, EAC6 and ECC3.