© Semiconductor Components Industries, LLC, 2017
November, 2018 − Rev. 12
1 Publication Order Number:
NB3N5573/D
NB3N5573
Clock Generator, Crystal to
25 MHz, 100 MHz, 125 MHz,
200 MHz, 3.3 V, with Dual
HCSL
Description
The NB
3N5573 is a precision, low phase noise clock generator that
supports PCI Express and Ethernet requirements. The device accepts a
25 MHz fundamental mode parallel resonant crystal and generates a
differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz
clock frequencies. Outputs can interface with LVDS with proper
termination (See Figure 4).
This device is housed in 5.0 mm x 4.4 mm narrow body TSSOP 16
pin package.
Features
• Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
• External Loop Filter is Not Required
• HCSL Differential Output or LVDS with Proper Termination
• Four Selectable Multipliers of the Input Frequency
• Output Enable with Tri−State Outputs
• PCIe Gen1, Gen2, Gen3, Gen4, QPI, UPI Jitter Compliant
• Phase Noise: @ 100 MHz
Offset Noise Power
100 Hz −109.4 dBc
1 kHz −127.8 dBc
10 kHz −136.2 dBc
100 kHz −138.8 dBc
1 MHz −138.2 dBc
10 MHz −161.4 dBc
20 MHz −163.00 dBc
• Typical Period Jitter RMS of 1.5 ps
• Operating Range 3.3 V ±10%
• Industrial Temperature Range −40°C to +85°C
• These are Pb−Free Devices
Figure 1. NB3N5573 Simplified Logic Diagram
Phase
Detector
Charge
Pump
HSCL
Output
BM
Clock Buffer
Crystal Oscillator
CLK0
CLK0
X1/CLK
X2
VCO
25 MHz Clock or
Crystal
GND
VDD
S0 S1 OE IREF
HSCL
Output
CLK1
CLK1
MARKING
DIAGRAM
TSSOP−16
DT SUFFIX
CASE 948F
www.onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
1
16
NB3N
5573
ALYWG
G
1
16
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
NB3N5573
www.onsemi.com
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S0
S1
NC
X1/CLK
X2
OE
GND
NC
VDD
CLK0
GND
VDD
IREF
CLK0
Figure 2. Pin Configuration (Top View)
CLK1
CLK1
Table 1. PIN DESCRIPTION
Pin Symbol I/O Description
1 S0 Input LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to V
DD
. See output select
table 2 for details.
2 S1 Input LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to V
DD
. See output select
Table 2 for details.
12, 16 V
DD
Power Supply Positive supply voltage pins are connected to +3.3 V supply voltage.
4 X1/CLK Input Crystal or Clock input. Connect to 25 MHz crystal source or single−ended clock.
5 X2 Input Crystal input. Connect to a 25 MHz crystal or leave unconnected for clock input.
6 OE Input Output enable tri−states output when connected to GND. Internal pullup resistor to V
DD
.
7, 13 GND Power Supply Ground 0 V. These pins provide GND return path for the devices.
9 I
REF
Output
Output current reference pin. Precision resistor (typ. 475 W) is connected to set the output
current.
11 CLK1 HCSL or
LVDS Output
Noninverted clock output. (For LVDS levels see Figure 4)
10 CLK1 HCSL or
LVDS Output
Inverted clock output. (For LVDS levels see Figure 4)
15 CLK0 HCSL or
LVDS Output
Noninverted clock output. (For LVDS levels see Figure 4)
14 CLK0 HCSL or
LVDS Output
Inverted clock output. (For LVDS levels see Figure 4)
3, 8 NC Do not connect
Table 2. OUTPUT FREQUENCY SELECT TABLE
WITH 25MHz CRYSTAL
S1* S0* CLK Multiplier f
CLKout
(MHz)
L L 1x 25
L H 4x 100
H L 5x 125
H H 8x 200
*Pins S1 and S0 default high when left open.
Recommended Crystal Parameters
Crystal Fundamental AT−Cut
Frequency 25 MHz
Load Capacitance 16−20 pF
Shunt Capacitance, C0 7 pF Max
Equivalent Series Resistance 50 W Max
Initial Accuracy at 25 °C ±20 ppm
Temperature Stability ±30 ppm
Aging ±20 ppm
Drive Level 100 mW Max