Jun. 2, 2021 © 2019 Transphorm Inc. Subject to change without notice.
tp65h150g4lsg.0v2 1
TP65H150G4LSG
650V SuperGaN
®
GaN FET in PQFN (source tab) Preliminary Datasheet
Key Specifications
V
DS
(V) min 650
V
DSS(TR)
(V) max 800
R
DS(on)
(mΩ) max* 180
Q
RR
(nC) typ 40
Q
G
(nC) typ 8
* Dynamic R
DS(on)
; see Figures 18 and 19
Features
• Gen IV technology
• JEDEC-qualified GaN technology
• Dynamic R
DS(on)eff
production tested
• Robust design, defined by
— Wide gate safety margin
— Transient over-voltage capability
• Very low Q
RR
• Reduced crossover loss
• RoHS compliant and Halogen-free packaging
Benefits
• Achieves increased efficiency in both hard- and soft-
switched circuits
— Increased power density
— Reduced system size and weight
— Overall lower system cost
• Easy to drive with commonly-used gate drivers
• GSD pin layout improves high speed design
Applications
• Consumer
• Power adapters
• Low power SMPS
• Lighting
Description
The TP65H150G4LSG 650V, 150mΩ Gallium Nitride (GaN)
FET is a normally-off device. It combines state-of-the-art high
voltage GaN HEMT and low voltage silicon MOSFET
technologies—offering superior reliability and performance.
The Gen IV SuperGaN
®
platform uses advanced epi and
patented design technologies to simplify manufacturability
while improving efficiency over silicon via lower gate charge,
output capacitance, crossover loss, and reverse recovery
charge.
Related Literature
• AN0003: Printed Circuit Board Layout and Probing
• AN0007: Recommendations for Vapor Phase Reflow
• AN0009: Recommended External Circuitry for GaN FETs
• AN0012: PQFN Tape and Reel Information
Product Series and Ordering Information
Part Number Package
Package
Configuration
TP65H150G4LSG-TR
*
8x8 PQFN Source
Cascode Device Structure Cascode Schematic Symbol
TP65H150G4LSG
PQFN
(top view)
* “-TR” suffix refers to tape and reel. Refer to AN0012 for details.
S
G
D
Jun. 2, 2021 transphormusa.com
tp65h150g4lsg.0v2 2
TP65H150G4LSG—Preliminary
Absolute Maximum Ratings (T
c
=25°C unless otherwise stated.)
Symbol Parameter Limit Value Unit
V
DSS
Drain to source voltage (T
J
= -55°C to 150°C) 650
V V
DSS(TR)
Transient drain to source voltage
a
800
V
GSS
Gate to source voltage ±20
P
D
Maximum power dissipation @T
C
=25°C 52 W
I
D
Continuous drain current @T
C
=25°C
b
13 A
Continuous drain current @T
C
=100°C
b
8.4 A
I
DM
Pulsed drain current (pulse width: 10µs) 60 A
T
C
Operating temperature
Case -55 to +150 °C
T
J
Junction -55 to +150 °C
T
S
Storage temperature -55 to +150 °C
T
SOLD
Reflow soldering temperature
c
260 °C
Notes:
a. In off-state, spike duty cycle D<0.01, spike duration <30s. Nonrepetitive.
b. For increased stability at high current operation, see Circuit Implementation on page 3
c. Reflow MSL3
Thermal Resistance
Symbol Parameter Typical Unit
R
ΘJC
Junction-to-case 2.4 °C/W
R
ΘJA
Junction-to-ambient
d
50 °C/W
Notes:
d. Device on one layer epoxy PCB for drain connection (vertical and without air stream cooling, with 6cm
2
copper area and 70µm thickness)