Silanna Semiconductor Proprietary and Confidential
Patents: www.powerdensity.com/patents
Page 1
Document 10853 Ver. 4.2
Flyback PWM Controller with Integrated Active Clamp Circuit
Features
▪ Integrated UHV Active Clamp FET, Active
Clamp Driver and Start-up Regulator
▪ Capable of Over 93.5% Efficiency
▪ Flat Efficiency Across Universal (90 - 265 Vac)
Input Voltage and Load
▪ Tight Switching Frequency Regulation for
Improved Input EMI Filter Utilization
▪ Up to 140 kHz Switching Frequency Operation
▪ OptiMode™ Cycle-by-Cycle Adaptive Digital
Control
▪ Quasi-Resonant (QR), Valley Mode Switching
(VMS) for low EMI
▪ Multi-Mode Operation (Burst Mode, QR, VMS)
▪ QR Valley Mode Switching for low EMI
▪ Self-Tuning Valley Detection
▪ OTP, OVP, OCP, OOPP and OSCP
Protections
▪ <50 mW No Load Power Consumption
▪ Up to 33 W Output Power
▪ 16-pin SOIC Package
Applications
▪ High Power Density USB-PD AC/DC Power
Supplies
▪ High Efficiency USB-PD Power Adapters
Application Diagram
SZ1101
VBULK_S
CLMP_S
V5OUT GND
BOOT_CL
FB
SW
V10
ISNSGATE
TEMP
Auxiliary
Primary
V
BULK
Primary FET
V5OUT
VAUX_S
CLAMP
DGND
Figure 1: Active Clamp Flyback Controller
Product Description
The SZ1101 is an Active Clamp Flyback (ACF) PWM
Controller that integrates an adaptive digital PWM
controller and the following Ultra High-Voltage (UHV)
components: active clamp FET, active clamp driver and a
start-up regulator.
The device provides ease-of-design of a simple flyback
controller with all the benefits of an ACF design, including
recycling of the leakage inductance energy of the flyback
transformer and limiting the primary FET drain voltage
spike during the turn-off events. Employing Silanna’s
OptiModeTM digital control architecture, the SZ1101
adjusts the device’s mode of operation on a cycle-by-cycle
basis to maintain high efficiency, low EMI, fast dynamic
load regulation and other key power supply parameters in
response to varying line voltage and load.
Furthermore, the switching frequency is confined within a
tight frequency band for simplified EMI filtering. In addition,
adaptive digital control of active clamp operation enables
near ZVS turn-on of the primary FET and clamps the drain
voltage during the turn-off, thus further improving efficiency
and reducing EMI.
Unlike conventional ACF designs, tight tolerances of the
clamp capacitor and leakage inductance values are not
required for proper operation of the circuit in high volume
production. Moreover, a small 3.3 nF clamp capacitor is
sufficient to realize the benefits of ACF operation. The
SZ1101 is well suited for high efficiency and high-power
density USB-PD AC/DC power adapters, providing up to
33 W output power.
The SZ1101 is available in a space saving 16-pin SOIC
package.
Figure 2: Device Package Image
SZ1101
PRODUCT BRIEF SZ1101
Silanna Semiconductor Proprietary and
Confidential For more information:
www.powerdensity.com
Page 2
Document 10853 Ver. 4.2
Pinout
V10
FB
V5OUT
TEMP
VBULK_S
CLMP_S
VAUX_S
GATE
ISNS
SW
BOOT_CL
CLAMP
GND
1
3
4
6
7
8 9
10
11
12
13
14
15
16
DGND
Figure 3. SZ1101, SOIC16-2L, 1.27 mm Pitch Package Pinout – Device Top View
Pin Descriptions
Pin #
Name
Voltage Category
(Vdc)
Description
1
CLAMP
UHV (620V)
Drain of Active Clamp (ACL) FET. Connect through a clamp capacitor to
VBULK
3
SW
UHV (620V)
Switching node. Connect to transformer primary and Drain of the Primary N-
FET
4
BOOT_CL
UHV (620V)
Bootstrap supply input for internal ACL FET driver. Connect a bootstrap
diode from V5OUT to BOOT_CL and a bootstrap capacitor from SW node
6
GND
LV (0)
Power ground pin for the IC. Connect to GND
7
V10
LV (10V)
Supply voltage input, 9.5 V nominal
8
GATE
LV (10V)
Gate driver output for Primary N-FET (refer to V10)
9
TEMP
LV (5V)
External NTC temperature sensor input
10
DGND
LV (0)
Digital ground. Connect to GND
11
ISNS
LV (5V)
Current sense input. Connect to the positive terminal of the current shunt
resistor
12
FB
LV (5V)
Output voltage error input (feedback). Connect to the Optocoupler collector
and pull up to V5OUT
13
V5OUT
LV (5V)
Output and decoupling pin for the internal +5 V supply
14
VAUX_S
LV: (5V)
Auxiliary winding sense input for QR operation. Connect the auxiliary positive
terminal to this pin via a resistor divider
15
VBULK_S
LV: (5V)
VBULK sense input. Connect to the rectified input voltage (VBULK) via a
resistor divider
16
CLMP_S
LV: (5V)
Active Clamp sense input. Connect to CLAMP via a resistive divider