Embedded USB Host/Slave Controller
CBM9001A
Datasheet
专芯发展
•
用芯服务
•
创芯未来
www. corebai. com
DMA
Interface
INTERRUPT
CONTROLLER
PROCESSOR
INTERFACE
256 Byte RAM
BUFFERS
&
CONTROL
REGISTERS
USB
Root
HUB
XCVRS
SERIAL
INTERFACE
ENGINE
Features
■
First USB Host/Slave controller for embedded systems in the
market with a standard microprocessor bus interface
■
Supports both full speed (12 Mbps) and low speed (1.5 Mbps)
USB transfer in both master and slave modes
■
Conforms to USB Specification 1.1 for full- and low speed
■
Operates as a single USB host or slave under software control
■
Automatic detection of either low- or full-speed devices
■
8-bit bidirectional data, port I/O (DMA supported in slave mode)
■
On-chip SIE and USB transceivers
■
On-chip single root HUB support
■
256-byte internal SRAM buffer
■
Ping-pong buffers for improved performance
■
Operates from 12 or 48 MHz crystal or oscillator (built-in DPLL)
■
5 V-tolerant interface
■
Suspend/resume, wake up, and low-power modes are
supported
■
Auto-generation of SOF and CRC5/16
■
Auto-address increment mode, saves memory READ/WRITE
cycles
■
Development kit including source code drivers is available
■
3.3-V power source, 0.35 micron CMOS technology
■
Available in 48-pin TQFP package
Logic Block Diagram
Functional Description
The CBM9001A is an Embedded USB Host/Slave Controller
capable of communicating in either full speed or low speed. The
CBM9001A interfaces to devices such as microprocessors,
micro- controllers, DSPs, or directly to a variety of buses such
as ISA, PCMCIA, and others. The CBM9001A USB Host
Controller conforms to USB Specification 1.1.
The CBM9001A incorporates USB Serial Interface functionality
along with internal full or low speed transceivers. The
CBM9001A supports and operates in USB full speed mode at 12
Mbps, or in low-speed mode at 1.5 Mbps. When in host mode,
the CBM9001A is the master and controls the USB bus and the
devices that are connected to it. In peripheral mode, otherwise
known as a slave device, the CBM9001A operates as a variety
of full- or low-speed devices.
The CBM9001A data port and microprocessor interface provide
an 8-bit data path I/O or DMA bidirectional, with interrupt
support to allow easy interface to standard microprocessors or
microcontrollers such as Motorola or Intel CPUs and many
others. The CBM9001A has 256 bytes of internal RAM, which
is used for control registers and data buffers.
The available Pb-free package is a 48-pin (CBM9001A)
package. All packages operate at 3.3 VDC. The I/O interface
logic is 5 V-tolerant.
INTR
D
+
D-
nDRQ
nDACK
nWR
nRD
nCS
nRST
D0-7
X1 X2
Master/Slave
Controller
CLOCK
GENERATOR
Embedded USB Host/Slave Controller
CBM9001A
Datasheet
专芯发展 • 用芯服务 • 创芯未来 www. corebai. com
-2-
Functional Overview
Data Port, Microprocessor Interface
The CBM9001A
microprocessor interface provides an 8-bit
bidirectional data path along with appropriate control lines to
interface to external processors or controllers. Programmed I/O
or memory mapped I/O designs are supported through the 8-bit
interface, chip select, read and write input strobes, and a single
address line, A0.
Access to memory and control register space is a simple two
step process, requiring an address Write with A0 = ‘0’, followed
by a register/memory Read or Write cycle with address line
A0 = ‘1’.
In addition, a DMA bidirectional interface in slave mode
is
available with handshake signals such as nDRQ, nDACK, nWR,
nRD, nCS and INTRQ.
The CBM9001A WRITE or READ operation terminates when
either nWR or nCS goes inactive. For devices interfacing to the
CBM9001A that deactivate the Chip Select nCS before the
Write nWR, the data hold timing must be measured from the
nCS and
is the same value as specified. Therefore, both Intel
®
- and
Motorola-type CPUs work easily with the CBM9001A without
any external glue logic requirements.
DMA Controller (slave mode only)
In applications that require transfers of large amount of data,
such as scanner interfaces, the CBM9001A provides a DMA
interface. This interface supports DMA READ or WRITE
transfers to the CBM9001A internal RAM buffer, it is done
through the microprocessor data bus via two control lines
(nDRQ - Data Request and nDACK - Data Acknowledge), along
with the nWR line and controls the data flow into the
CBM9001A. The CBM9001A has a count register that allows
selection of programmable block sizes for DMA transfer. The
control signals, both nDRQ and nDACK, are designed for
compatibility with standard DMA interfaces.
Interrupt Controller
The CBM9001A interrupt controller provides a single output
signal (INTRQ) that is activated by a number of programmable
events that may occur as a result of USB activity. Control and
status registers are provided to allow the user to select single
or multiple events, which generate an interrupt (assert INTRQ)
and let the user view interrupt status. The interrupts are
cleared by writing to the Interrupt Status Register.