Development Board
EPC9094
Quick Start Guide
200 V Half-bridge with Gate Drive, Using EPC2054
Revision 1.0
QUICK START GUIDE
EPC9094
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 2
DESCRIPTION
The EPC9094 is a half bridge development board with onboard gate
driver, featuring the 200 V rated EPC2054 GaN eld eect transistor (FET).
The purpose of this development board is to simplify the evaluation
process of the EPC2054 by including all the critical components on a
single board that can be easily connected into the majority of existing
converter topologies.
The EPC9094 evaluation board measures 2” x 2” and contains two
EPC2054 GaN FETs in a half bridge conguration. The EPC9094 features
the On-Semi NCP51820 gate driver. The board also contains all critical
components and the layout supports optimal switching performance.
There are also various probe points to facilitate simple waveform
measurement and eciency calculation. A block diagram of the circuit
is given in gure 1.
For more information on EPC2054 please refer to the datasheet
available from EPC at www.epc-co.com. The datasheet should be read in
conjunction with this quick start guide.
Table 1: Performance Summary (T
A
= 25°C) EPC9094
Symbol Parameter Conditions Min Nominal Max Units
V
DD
Gate Drive Input
Supply Range
10 15 V
V
IN
Bus Input Voltage
Range
(1)
160
I
OUT
Switch Node Output
Current
(2)
2 A
V
PWM
PWM Logic Input
Voltage Threshold
(3)
Input ‘High’ 3.5 5.5 V
Input ‘Low’ 0 1.5
V
EN
Enable Logic Input
Voltage Threshold
(3)
Input ‘High’ 3.5 5.5 V
Input ‘Low’ 0 1.5
PWM ‘High’ State
Input Pulse Width
V
PWM
rise and fall
time < 10ns
50 ns
PWM ‘Low’ State
Input Pulse Width
(4)
V
PWM
rise and fall
time < 10ns
200
(1) Maximum input voltage depends on inductive loading, maximum switch node ringing
must be kept under 200 V for EPC2054.
(2) Maximum current depends on die temperature – actual maximum current is aected by
switching frequency, bus voltage and thermal cooling.
(3) When using the on board logic buers, refer to the NCP51820 datasheet when bypass
-
ing the logic buers.
(4) Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
EPC9094 development board
Back view
Front view
Figure 1: Block diagram of EPC9094 development board
V
DD
V
IN
Q
1
Q
2
C
Bypass
PWM1
EN
GND jumper
EN
Default
- Independent PWM
- No-X conduction protection
5 V
GND
C
out
Gate driver
Out
PGND
PWM2
L
1
Level
shift
LDO
LDO
Hin
Lin
DT
LDO
Level
shift
D
BTST
LDO
Logic
Gate drive
regulator
Logic and
dead-time
adjust
*
*