eGaN® TECHNOLOGY

How2AppNote 012

Motivation

Enhancement-mode gallium nitride (eGaN®) FETs offer high power-

density capabilities with ultra-fast switching and low on-resistance, all in

a compact form factor. However, the achievable power levels are limited

by thermal overheating due to the extreme heat-flux densities. If not

managed properly, the generated heat can result in excessive self-heating

and elevated temperatures that compromise reliability and performance.

For that reason, thermal management strategies are essential for high-

power devices, and with chip-scale packaging of eGaN® FETs, many

design advantages can be leveraged at the board-side and the backside

(i.e., case) for improved heat dissipation.

This application note presents simple thermal management guidelines

to enhance heat conductance from the GaN FETs and optimize thermal

performance. In addition, a case study is presented with simple and

effective thermal management solutions for the cooling of a development

board with two active GaN FETs.

Overview

Packaged electronic devices dissipate generated heat through two

main heat conduction paths – to the printed circuit board (PCB) at the

board-side and to the case at the backside, both of which can benefit

from thermal management strategies. The first thermal resistances to

heat dissipation encountered are at the FET construction level from the

junction to the board (R

θJB

) and from the junction to the case (R

θJC

The thermal resistance to heat conduction is generally described as:

Where,

θJX

, alternatively, Θ

(°C/W or K/W) = thermal resistance from junction

to a reference location X

(°C or K) = device junction temperature in steady state conditions

(°C or K) = temperature of reference location (board (B), case (C), or

ambient (A))

P (W) = power dissipated in the device

These two thermal resistances differ for each FET since they depend

on the device construction and on the thermal conductivity of the

materials used. For wafer-level chip-scale packaged (WLCSP) GaN

FETs, the thermal resistance to case is lower than silicon devices

(Figure 1), and thus the junction-to-case path provides good thermal

conductance. With simple methods that ensure optimal thermal

practice, both R

θJC

and R

θJB

can be used to significant advantage.

Junction-to-Board Thermal Improvement Strategies

The maximum temperature rise (in °C or K), and the resulting overall

thermal resistance (in K/W), are reported for the maximum temperature

at the device junction, in reference to an ambient temperature in still

air (R

θJA

) or in moving air (R

θJMA

). The thermal resistance to the board is

one component in a network of heat conduction paths that determines

the overall self-heating in a GaN FET device.

Thermal Management of eGaN

FETs

EFFICIENT POWER CONVERSION

Figure 1: Junction to case and to board thermal

resistance comparison between GaN and silicon devices.

θJX

= T

– T

3.0

2.5

2.0

1.5

1.0

0.5

0 10

θJB

(°C/W)R

θJC

(°C/W)

Device Area (mm

)

Device Area (mm

)

30 40

0 10 20 30 40

3.0

2.5

2.0

1.5

1.0

0.5

Silicon

GaN

Silicon

GaN

How2AppNote 012

eGaN® TECHNOLOGY

Figure 3: PCB thermal performance comparison between dierent congurations that include thermal vias near and underneath the FET pads.

The simplified circuit model in Figure 2 represents the main heat

conduction paths from the junction to ambient within a standard PCB

layout with two FETs. Since the FET area is much smaller than that of

the PCB, the heat dissipated from the FET to ambient through the case

is minimal and thus the thermal resistance R

θCA

is large. As a result,

without any back-side cooling, the main heat dissipation path from the

FET is through the PCB, which is why we must ensure good thermal

conductance at the board-side.

Heat conduction from the FET into the board is carried mainly by the

copper traces within the conducting layers of the PCB. Designing

thicker copper traces for low electrical resistance also benefits thermal

resistance and provides a high heat-conductance medium at each

layer of the PCB. For example, a 2-ounce (oz) copper layer has twice the

conductance of 1 oz copper layer in the lateral directions. Moreover,

the in-plane heat conductance is proportionally dependent on the

number of layers, where more layers offer more paths to dissipate heat.

In the through-plane direction, the insulating dielectric layers

separating the copper layers have a low thermal conductivity and

thus obstruct heat dissipation. This issue can be partially overcome

by placing vias within or near the FETs to provide a high thermal

conductivity path that bridges the dielectric layers and carries the

generated heat into the inner copper layers of the PCB. The inner

layers, in turn, contribute to heat spreading, further decreasing the

thermal resistance into the board (R

θJB

) and eventually into ambient

air (R

θJA

). Strategically placed thermal vias near or under the FET

pads can reduce self-heating (ΔT) by up to 33% as shown in detailed

thermal simulations (Figure 3).

The vias modeled in the simulations have a Via-in-Pad-Plated-Over (VIPPO)

construction which is described in the insert.

Figure 2: Simplied thermal resistance network model showing main heat

conduction paths and associated temperature nodes for a FET layout.

θCA1

θJC1

θBA1

θJB1

θB12

θBA2

θJB2

θCA2

θJC2

amb

PCB

FET 1 FET 2

Side vias Vias under bumpNo vias

θ, Junction-to-Moving Air, (JMA)

= 45 K/W R

θ,JMA

= 35 K/W (22% ) R

θ,JMA

= 30 K/W (33% )

Via locations

Side vias

Vias under bump

No vias

Soldermask

(tented)

Plated

Over

Via wall

Via ll

Via-In-Pad-Plated-Over (VIPPO)

• Wall thickness = 0.78 mil per IPC

standard class 2

• Hole diameter (typical) = 7.8 mil

• Annular ring =

13.8 mil diameter min.

• Plated over

• Non-conductive filled

• Tented on both sides of the board

• Used for under bump and close to

component pads

• Usable up to 2 oz (2.8 mil / 70 µm)

copper thickness