ISSI DDR2 SDRAM Design Considerations Guide

Introduction

This is a general board design considerations guideline for ISSI DDR2 SDRAM, especially for point to

point applications. Chipset companies may have their own application notes for designing using

DDR2 DRAM. ISSI recommends following the chipset company’s guidelines first.

PCB Layout Guidelines

50–60Ω impedance (ZO) is recommended for all traces. FR-4 is commonly used for the dielectric

material. The board thickness and trace width and thickness should be adjusted to match the

impedance. Trace lengths are also influential, and they should be determined by simulation for each

signal group and verified in test.

In general, ISSI recommends the minimum rules for traces in the board as shown below for the

minimization of crosstalk. These rules are based on the assumption of a signal slew rate of 1V/1ns. In

slower applications, cross-talk generally is not a factor, and closer spacing may be allowed.

1. Signals from the same net group should be routed on the same layer.

2. Signals from Byte group, such as DQS, DM and 8 bits of DQ, must be routed in the same layer

3. The deviation of signal propagation delay is dependent on the timing budget on the application.

The following values in the table are good examples at the start of a design.

Signals on Net

Maximum deviation of signal

propagation difference.

Maximum deviation

of trace length.

All data, address and command signals

must be followed within this variation.

±50ps

±6.635mm(261mil)

Between CK and CK#.

Between DQSn and DQS#n

±2 ps

±0.254mm (10mil)

Between one clock pair and another clock

pair, eg) CK/CK# and DQSn/DQS#n

±5 ps

±0.635mm(25mil)

Between signals within byte

group(DQS,DM,8bits of DQ)

±10ps

±1.270mm(50mil)

4. Minimum trace width is 0.13mm (5mil).

5. Intranet spacing, the distance between two adjacent traces within a net, is 0.2mm (7mil).

6. Internet spacing, the distance between the two outermost signals of different signal group is

15mil. The same rule applies between one clock pair and another clock pair.

7. Differential clocks should be routed in parallel and keep the trace length short.

8. Differential clocks must be routed on the same layer and placed on an internal layer minimize the

noise.

9. Keep the internet spacing rule between CKE and CK/CK#

REF

control

Setup and hold time margin could be reduced if VREF has noise. VREF integrity should be provided by

the user to optimize noise margin in the system. The VREF level is expected to track variations in

VDDQ , and the peak-to-peak noise should be met with specification:

1. 1KΩ±1%/1KΩ±1%/ from VDDQ power panel

2. Place a 0.1uF capacitor between VREF and VDDQ

3. Place a 0.1uF capacitor between VREF and VSSQ

4. VREF should have a minimum trace to reduce inductance

5. VREF should keep a distance from other signals to reduce the potential of a decoupling effect

EMI and Termination

The DDR2 SDRAM offers full drive strength and reduced drive strength, as recommended by JEDEC.

They are controlled by EMRS setting, during initialization. The full drive has an output impedance of

about 18Ω and the reduced drive has an output impedance of about 40Ω. Selecting the drive

strength should be based on the simulation result.

DDR2 SDRAM offers ODT features for DM, DQS and DQs pins. With a short trace length (less than

5cm), it may not required. Matching impedance by using a serial resistor can also improve the

performance, but ODT control is generally recommended for better signal integrity. If a serial resistor

is used, 10-33Ω serial resistor can be used and located to the middle portion of the trace.

For the command and address inputs, typically, 10~33Ω serial resistor termination is used and closely

located to the transmitting device, if it is required.

For clock inputs, ISSI doesn’t recommend any termination, except adding 100~120Ω between

differential clocks. The trace needs to be as short as possible to reduce noise.

If any signal trace is longer than 5cm, R

to V

will be recommended.

Power Supply and Decoupling Capacitors

In most cases, to specifically decouple the DRAM, it is popular and effective to use one or two 10uF

or 4.7uf bulk capacitors near LDO and several 0.1uF decoupling capacitors close to the DDR2.

However, this recommendation may not be sufficient to cover the wide variety of applications using

DDR2 today. Because of this, ISSI recommends comprehensive board simulations to ensure the

optimal power supply conditions in DDR2 memory applications.