RA2L1 Group
Renesas Microcontrollers
Ultra low power 48 MHz Arm
®
Cortex
®
-M23 core, up to 256-KB code flash memory, 32 KB SRAM, Capacitive Sensing Unit 2
(CTSU), 12-bit A/D Converter, 12-bit D/A Converter, Security and Safety features.
Features
R01DS0385EJ0100
Rev
.1.00
Aug 06, 2020
■ Arm Cortex-M23 Core
● Armv8-M architecture
● Maximum operating frequency:
48 MHz
● Arm Memory Protection Unit (Arm MPU) with 8 regions
● Debug and Trace: DWT, FPB, CoreSight
™
MTB-M23
● CoreSight Debug Port: SW-DP
■ Memory
● Up to 256-KB code flash memory
● 8-KB data flash memory (100,000 program/erase (P/E) cycles)
● 32 KB SRAM
● Memory protection units
● 128-bit unique ID
■ Connectivity
●
Serial Communications Interface (SCI) × 5
– Asynchronous interfaces
– 8-bit clock synchronous interface
– Simple IIC
– Simple SPI
��� Smart card interface
● Serial Peripheral Interface (SPI) × 2
● I
2
C bus interface (IIC) × 2
● CAN module (CAN)
■ Analog
● 12-bit A/D Converter (ADC12)
●
12-bit D/A Converter (DAC12)
● Low-Power Analog Comparator (ACMPLP) × 2
● Temperature Sensor (TSN)
■ Timers
● General PWM Timer 32-bit (GPT32) × 4
● General PWM Timer 16-bit (GPT16) × 6
● Low Power Asynchronous General Purpose Timer (AGT) × 2
●
Watchdog Timer (WDT)
■ Safety
●
ECC in SRAM
● SRAM parity error check
● Flash area protection
● ADC self-diagnosis function
● Clock Frequency Accuracy Measurement Circuit (CAC)
● Cyclic Redundancy Check (CRC) calculator
●
Data Operation Circuit (DOC)
● Port Output Enable for GPT (POEG)
● Independent Watchdog Timer (IWDT)
● GPIO readback level detection
● Register write protection
● Main oscillator stop detection
● Illegal memory access
■ Security and Encryption
●
AES128/256
● True Random Number Generator (TRNG)
■ System and Power Management
● Low power modes
● Switching regulator
● Realtime Clock (RTC)
● Event Link Controller (ELC)
● Data Transfer Controller (DTC)
●
Key Interrupt Function (KINT)
● Power-on reset
● Low Voltage Detection (LVD) with voltage settings
■ Human Machine Interface (HMI)
● Capacitive Sensing Unit 2 (CTSU)
■ Multiple Clock Sources
● Main clock oscillator (MOSC) （1 to 20 MHz）
● Sub-clock oscillator (SOSC) (32.768 kHz)
● High-speed on-chip oscillator (HOCO) (24/32/48/64 MHz)
● Middle-speed on-chip oscillator (MOCO) (8 MHz)
● Low-speed on-chip oscillator (LOCO) (32.768 kHz)
● Clock trim function for HOCO/MOCO/LOCO
● IWDT
-dedicated on-chip oscillator (15 kHz)
● Clock out support
■ Up to 85 pins for general I/O ports
● 5-V tolerance, open drain, input pull-up
■ Operating Voltage
● VCC: 1.6 to 5.5 V
■ Operating Temperature and Packages
● Ta = -40℃ to +85℃
– 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
– 80-pin LQFP (12 mm × 12 mm, 0.5 mm pitch)
–
64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
– 48-pin LFQFP (7 mm × 7 mm, 0.50 mm pitch)
– 48-pin HWQFN (7 mm × 7 mm, 0.50 mm pitch)
● Ta = -40℃ to +105℃
– 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
– 80-pin LQFP (12 mm × 12 mm, 0.5 mm pitch)
– 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
–
48-pin LFQFP (7 mm × 7 mm, 0.50 mm pitch)
– 48-pin HWQFN (7 mm × 7 mm, 0.50 mm pitch)
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 1 of 110
Datasheet
1. Overview
The MCU integrates multiple series of software- and pin-compatible Arm
®
-based 32-bit cores that share a common set of
Renesas peripherals to facilitate design scalability.
The MCU in this series incorporates an energy-efficient Arm Cortex
®
-M23 32-bit core, that is particularly well suited for
cost-sensitive and low-power applications, with the following features:
●
Up to 256-KB code flash memory
●
32-KB SRAM
●
12-bit A/D Converter (ADC12)
●
12-bit D/A Converter (DAC12)
●
Security features
1.1 Function Outline
Table 1.1 Arm core
Feature Functional description
Arm Cortex-M23 core ● Maximum operating frequency: up to 48 MHz
● Arm Cortex-M23 core:
– Revision: r1p0-00rel0
– Armv8-M architecture profile
– Single-cycle integer multiplier
– 19-cycle integer divider
● Arm Memory Protection Unit (Arm MPU):
– Armv8 Protected Memory System Architecture
– 8 protect regions
● SysTick timer:
– Driven by SYSTICCLK (LOCO) or ICLK
Table 1.2 Memory
Feature Functional description
Code flash memory Maximum 256 KB of code flash memory.
Data flash memory 8 KB of data flash memory.
Option-setting memory The option-setting memory determines the state of the MCU after a reset.
SRAM On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC).
Table 1.3 System (1 of 2)
Feature Functional description
Operating modes Two operating modes:
● Single-chip mode
● SCI boot mode
Resets The MCU provides 13 resets. lists the reset names and sources.
Low Voltage Detection (LVD) The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The
detection level can be selected by register settings. The LVD module consists of three separate
voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level
input to the VCC pin. LVD registers allow your application to configure detection of VCC changes
at various voltage thresholds.
See section x, Low Voltage Detection (LVD).
Clocks ● Main clock oscillator (MOSC)
● Sub-clock oscillator (SOSC)
● High-speed on-chip oscillator (HOCO)
● Middle-speed on-chip oscillator (MOCO)
● Low-speed on-chip oscillator (LOCO)
● IWDT-dedicated on-chip oscillator (IWDTLOCO)
● Clock out support
RA2L1 Datasheet 1. Overview
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 2 of 110