RA4M3 Group
Renesas Microcontrollers
Leading-performance 100 MHz Arm Cortex-M33 core, up to 1 MB code flash memory with background and SWAP operation,
8 KB Data flash memory
, and 128 KB SRAM with Parity/ECC. High-integration with USB 2.0 Full-Speed, SDHI, Quad SPI,
and advanced analog. Integrated Secure Crypto Engine with cryptography accelerators, key management support, tamper
detection and power analysis resistance in concert with Arm TrustZone for integrated secure element functionality.
Features
R01DS0368EJ0120
Rev
.1.20
Dec 2, 2020
■
Arm
®
Cortex
®
-M33 Core
● Armv8-M architecture with the main extension
● Maximum operating frequency:
100 MHz
● Arm Memory Protection Unit (Arm MPU)
– Protected Memory System Architecture (PMSAv8)
– Secure MPU (MPU_S): 8 regions
– Non-secure MPU (MPU_NS): 8 regions
● SysTick timer
– Embeds two Systick timers: Secure and Non-secure instance
– Driven by LOCO or system clock
● CoreSight
™
ETM-M33
■ Memory
● Up to 1-MB code flash memory
● 8-KB data flash memory (100,000 program/erase (P/E) cycles)
●
128-KB SRAM
■ Connectivity
● Serial Communications Interface (SCI) × 6
– Asynchronous interfaces
– 8-bit clock synchronous interface
– Smart card interface
– Simple IIC
– Simple SPI
–
Manchester coding (SCI3, SCI4)
● I
2
C bus interface (IIC) × 2
●
Serial Peripheral Interface (SPI)
● Quad Serial Peripheral Interface (QSPI)
● USB 2.0 Full-Speed Module (USBFS)
● Control Area Network module (CAN) × 2
● SD/MMC Host Interface (SDHI)
● Serial Sound Interface Enhanced (SSIE)
■ Analog
● 12-bit A/D Converter (ADC12) × 2
●
12-bit D/A Converter (DAC12) × 2
● Temperature Sensor (TSN)
■ Timers
● General PWM Timer 32-bit (GPT32) × 4
● General PWM Timer 16-bit (GPT16) × 4
● Low Power Asynchronous General Purpose Timer (AGT) × 6
■ Security and Encryption
● Secure Crypto Engine 9
– Symmetric algorithms: AES
–
Asymmetric algorithms: RSA, ECC, and DSA
– Hash-value generation: SHA224, SHA256, GHASH
– 128-bit unique ID
● Arm
®
TrustZone
®
– Up to three regions for the code flash
– Up to two regions for the data flash
– Up to three regions for the SRAM
– Individual secure or non-secure security attribution for each
peripheral
● Device lifecyle management
●
Pin function
– Up to three tamper pins
– Secure pin multiplexing
■ System and Power Management
● Low power modes
● Battery backup function (VBATT)
● Realtime Clock (RTC) with calendar and VBATT support
● Event Link Controller (ELC)
●
Data Transfer Controller (DTC)
● DMA Controller (DMAC) × 8
● Power-on reset
● Low Voltage Detection (LVD) with voltage settings
● Watchdog Timer (WDT)
● Independent W
atchdog Timer (IWDT)
■ Human Machine Interface (HMI)
● Capacitive Touch Sensing Unit (CTSU)
■ Multiple Clock Sources
● Main clock oscillator (MOSC) (8 to 24 MHz)
● Sub-clock oscillator (SOSC) (32.768 kHz)
● High-speed on-chip oscillator (HOCO) (16/18/20 MHz)
● Middle-speed on-chip oscillator (MOCO) (8 MHz)
● Low-speed on-chip oscillator (LOCO) (32.768 kHz)
● IWDT-dedicated on-chip oscillator (15 kHz)
● Clock trim function for HOCO/MOCO/LOCO
● PLL/PLL2
●
Clock out support
■ General-Purpose I/O Ports
● 5-V tolerance, open drain, input pull-up, switchable driving ability
■ Operating Voltage
● VCC: 2.7 to 3.6 V
■ Operating Temperature and Packages
● Ta = -40℃ to +105℃
– 144-pin LQFP (20 mm × 20 mm, 0.5 mm pitch)
– 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
– 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 1 of 92
Datasheet
1. Overview
The MCU integrates multiple series of software- and pin-compatible Arm
®
-based 32-bit cores that share a common set of
Renesas peripherals to facilitate design scalability and efficient platform-based product development.
The MCU in this series incorporates a high-performance Arm Cortex
®
-M33 core running up to 100 MHz with the following
features:
●
Up to 1 MB code flash memory
●
128 KB SRAM
●
Quad Serial Peripheral Interface (QSPI)
●
USBFS, SD/MMC Host Interface
●
Capacitive Touch Sensing Unit (CTSU)
●
Analog peripherals
●
Security and safety features
1.1 Function Outline
Table 1.1 Arm core
Feature Functional description
Arm Cortex-M33 core ● Maximum operating frequency: up to 100 MHz
● Arm Cortex-M33 core:
– Armv8-M architecture with security extension
– Revision: r0p4-00rel0
● Arm Memory Protection Unit (Arm MPU)
– Protected Memory System Architecture (PMSAv8)
– Secure MPU (MPU_S): 8 regions
– Non-secure MPU (MPU_NS): 8 regions
● SysTick timer
– Embeds two Systick timers: Secure and Non-secure instance
– Driven by SysTick timer clock (SYSTICCLK) or system clock (ICLK)
● CoreSight
™
ETM-M33
Table 1.2 Memory
Feature Functional description
Code flash memory Maximum 1 MB of code flash memory.
Data flash memory 8 KB of data flash memory.
Option-setting memory The option-setting memory determines the state of the MCU after a reset.
SRAM On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC).
Table 1.3 System (1 of 2)
Functional description
Operating modes Two operating modes:
● Single-chip mode
● SCI/USB boot mode
Resets The MCU provides 14 resets.
Low Voltage Detection (LVD) The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The
detection level can be selected by register settings. The LVD module consists of three separate
voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level
input to the VCC pin. LVD registers allow your application to configure detection of VCC changes
at various voltage thresholds.
RA4M3 Datasheet 1. Overview
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 2 of 92