High Performance
Serial MRAM Memory
M1004204/M1008204/ M1016204
M3004204/M3008204/M3
016204
Apr.16.20
Page 1
Description
Mxxxx204 is a magneto-resistive random-access memory
(MRAM). It is offered in density ranging from 4Mbit to 16Mbit.
MRAM technology is analogous to Flash technology with SRAM
compatible read/write timings (Persistent SRAM, P-SR AM). Data is
always non-volatile with 10
16
write cycles endurance and greater
than 20-year retention @85°C.
MRAM is a true random-access memory; allowing both reads and
writes to occur randomly in memory. MRAM is ideal for applicatio ns
that must store and retrieve data without incurring large latency
penalties. It offers low latency, low power, infinite endurance and
scalable non-volatile memory technology.
Mxxxx204 is available in small footprint 8-pad DFN (WSON) and 8-
pin SOIC packages. These packages are compatible with similar
low-power volatile and non -volatile products.
Mxxxx204 is offered with industrial (-40°C to 85°C) and i ndustrial
plus (-40°C to 105°C) operat ing temperature ranges.
Typical Applications
• Ideal for applications that must store and retrieve data
without incurring large latency penalties.
• Factory Automation
• Multifunction Printers
• Industrial Control And Monitoring
• Medical Diagnostics
• Data Switches And Routers
Block Diagram
Features
Interface
• Serial Peripheral Interface QSPI (4-4-4)
• Single Data Rate Mode: 108 MHz
• Double Data Rate Mode: 54MHz
Technology
• 40nm pMTJ STT-MRAM
• Data Endurance: 10
16
write cycles
• Data Retention: 20 years @ 85°C
Density
• 4Mb, 8Mb, 16Mb
Operating Voltage Range
• VCC: 1.71V – 2.00V
• VCC: 2.70V – 3.60V
Operating Temperature Ran ge
• Industrial: -40°C to 85°C
• Industrial Plus: -40°C to 105°C
Packages
• 8-pad DFN (WSON) (5.0mm x 6.0mm)
• 8-pin SOIC (5.2mm x 5.2mm)
Data Protection
• Hardware Based: Write Protect Pin (WP#)
• Software Based: Address Range Selectable through
Configuration bits (Top/Bottom, Block Protect[2:0])
Identification
• 64-bit Unique ID
• 64-bit User Programmable Serial Number
Augmented Storage Array
• 256-byte User Programmab le with Write Protection
Supports JEDEC Reset
RoHS Compliant
Regulator
MRAM
Array
MRAM
Array
Command
&
Control
MRAM
Array
Row Decoder
Column
Decoder
Data Buffer
Serial
I/Os
Address Reg ister
Status Register
Command Register
High Voltage
Generator
CS#
WP# / IO[2]
SI / IO[0]
CLK
IO[3]
SO / IO[1]
V
CC
V
SS
M1004204/M1008204/M1016204
M3004204/M3008204/M3016204
Apr.16.20
Page 2
Contents
1. Performance ............................................................................................................................................................................................3
2. General Descr i ption ...............................................................................................................................................................................3
3. Ordering Options ....................................................................................................................................................................................4
3.1 Valid Combinations — Standard .........................................................................................................................................................4
4. Signal Descri pt ion and Assignment ..................................................................................................................................................7
5. Package Options ....................................................................................................................................................................................9
5.1 8-Pad DFN (WSON) (Top View) ..........................................................................................................................................................9
5.2 8-Pin SOIC (Top View) ........................................................................................................................................................................9
6. Package Draw ings ...............................................................................................................................................................................10
6.1 8-Pad DFN (WSON) ..........................................................................................................................................................................10
6.2 8-Pin SOIC ........................................................................................................................................................................................11
7. Architecture ............................................................................................................................................................................................12
8. Device Initialization ..............................................................................................................................................................................14
9. Memory Map ..........................................................................................................................................................................................16
10. Augm ent ed Storage Array Map .......................................................................................................................................................16
11. Register Addresses .............................................................................................................................................................................16
12. Register Map..........................................................................................................................................................................................17
12.1 Status Register / Device Protection Register (Read/Write) ...............................................................................................................17
12.2 Augmented Storage Array Protection Register (Read/Write) ............................................................................................................18
12.3 Device Identification Register (Read O nly) ........................................................................................................................................19
12.4 Serial Number Register (Read/ Write) ................................................................................................................................................19
12.5 Unique Identification Register (Read On ly) .......................................................................................................................................19
12.6 Configuration Register 1 (Read/Write)...............................................................................................................................................20
12.7 Configuration Register 2 (Read/Write)...............................................................................................................................................21
12.8 Configuration Register 3 (Read/Write)...............................................................................................................................................23
12.9 Configuration Register 4 (Read/Write)...............................................................................................................................................23
13. Inst ruction Set ........................................................................................................................................................................................24
14. Instruction Description and Structures ...........................................................................................................................................27
15. Electr ical Specifications ......................................................................................................................................................................38
15.1 CS# Operation & Timing ....................................................................................................................................................................41
15.2 Data Output Operation & Timing .......................................................................................................................................................43
15.3 WP# Operation & Timing ...................................................................................................................................................................44
Enter Deep Power Down Command (EDP – B9h) ............................................................................................................................45
Exit Deep Power Down Command (EXDPD - ABh) ..........................................................................................................................46
Enter Hibernate Command (EHBN – BAh) ........................................................................................................................................47
16. Revision History ..........................................................................................................................................................................................48