Features

R01DS0354EJ0110 Rev.1.10 Page 2 of 100

Mar 16, 2020

■ Arm Cortex-M23 Core

 Armv8-M architecture

 Maximum operating frequ e ncy: 48 MHz

 Arm

Memory Protection Unit (Arm MPU) with 8 regions

 Debug and Trace: DWT, FPB, and CoreSight™ MTB-M23

 CoreSight Debug Port: SW-DP

■ Memory

 Up to 256-KB code flash memory

 8-KB data flash memory (100,000 program/erase (P/E) cycles)

 Up to 32-KB SRAM

 Flash Cache (FCACHE)

 Memory Protection Unit (MPU)

 Memory Mirror Function (MMF)

 128-bit unique ID

■ Connectivity

 USB 2.0 Full-Speed (USBFS) module

- On-chip transceiver with voltage regulator

- Compliant with USB Battery Charging Specification 1.2

 Serial Communications Interface (SCI) × 3

- UART

- Simple IIC

- Simple SPI

 Serial Peripheral Interface (SPI) × 2

 I

C bus interface (IIC) × 2

 Controller Area Network (CAN) module

■ Analog

 16-bit A/D Converter (ADC16)

- 1.2 Msps

- Differential input mode

- Single-ended input mode

 24-bit Sigma-Delta A/D Converter (SDADC24)

- 15.6 ksps

- Differential input mode

- Single-ended input mode

 12-bit D/A Converter (DAC12)

 8-bit D/A Converter (DAC8) × 2

 High-Speed Analog Comparator (ACMPHS)

 Low-Power Analog Comparator (ACMPLP) × 2

 Operational Amplifier (OPAMP) × 3

 Temperature Sensor (TSN)

■ Timers

 General PWM Timer 32-bit (GPT32)

 General PWM Timer 16-bit (GPT16) × 6

 Asynchronous Genera l-Pu rp ose Tim er (AGT) × 2

 Watchdog Timer (WDT)

■ Safety

 Error Correction Code (ECC) in SRAM

 SRAM parity error check

 Flash area protection

 ADC self-diagnosis function

 Clock Frequency Accuracy Measurement Circuit (CAC)

 Cyclic Redundancy Check (CRC) calculator

 Data Operation Circuit (DOC)

 Port Output Enable for GPT (POEG)

 Independent Watchdog Timer (IWDT)

 GPIO readback level detection

 Register write protection

 Main oscillator stop detection

 Illegal memory access

■ System and Power Management

 Low power modes

 Realtime Clock (RTC)

 Event Link Controller (ELC)

 Data Transfer Controller (DTC)

 Key Interrupt Function (KINT)

 Power-on reset

 Low Voltage Detection (LVD) with voltage settings

■ Security and Encryption

 AES128/256

 True Random Number Gen erato r (T RNG)

■ Human Machine Interface (HMI)

 Capacitive Touch Sensing Unit (CTSU)

■ Multiple Clock Sources

 Main clock oscillator (MOSC)

(1 to 20 MHz when VCC = 2.4 to 5.5 V)

(1 to 8 MHz when VCC = 1.8 to 5.5 V)

(1 to 4 MHz when VCC = 1.6 to 5.5 V)

 Sub-clock oscillator (SOSC) (32.768 kHz)

 High-speed on-chip oscillator (HOCO)

(24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V)

(24, 32, 48 MHz when VCC = 1.8 to 5.5 V)

(24, 32 MHz when VCC = 1.6 to 5.5 V)

 Middle-speed on-chip oscillator (MOCO) (8 MHz)

 Low-speed on-chip oscillator (LOCO) (32.768 kHz)

 IWDT-dedicated on-chip oscillator (15 kHz)

 Clock trim function for HOCO/MOCO/LOCO

 Clock out support

■ General Purpose I/O Ports

 Up to 49 input/output pins

- Up to 3 CMOS input

- Up to 46 CMOS input/output

- Up to 9 input/output 5 V tolerant

- Up to 3 high current (20 mA)

■ Operating Voltage

 VCC: 1.6 to 5.5 V

■ Operating Temperature and Packages

 Ta = -40°C to +85°C

- 36-pin BGA (5 mm × 5 mm, 0.8 mm pitch)

 Ta = -40°C to +105°C

- 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)

- 32-pin LQFP (7 mm × 7 mm, 0. 8 mm pitch)

- 48-pin QFN (7 mm × 7 mm, 0.5 mm pitch)

- 40-pin QFN (6 mm × 6 mm, 0.5 mm pitch)

Ultra-low power 48-MHz Arm

Cortex

-M23 core, up to 256-KB code flash memory, 32-KB SRAM, Capacitive Touch

Sensing Unit, 16-bit A/D Converter, 24-bit sigma-delta A/D Converter, 12-bit D/A Converter, 8-bit D/A Converter,

Operational Amplifier, security and safety features.

Features

RA2A1 Group

Datasheet

Features