PL5500
High Efficiency 4-Switch Bidirectional Buck-Boost Controller
DS-PL5500-Rev. 1.0
www.powlicon.com
1 of 18
2018-08-18
© Powlicon Inc.
1 Features
Bidirectional single Inductor Buck-Boost Controller
for Step-Up/Step-Down DC/DC Conversion and
battery charge management
Bidirectional buck-boost operation to support
battery charging and discharging using OTG signal
Dynamical programming of input current, Output
current and Output voltage using PWM signal or
analog signal
1 Cell to 6 Cells battery charge management
2V to 32 V wide output range
Comprehensive protection features including
Output Short Protection (OSP), Cycle-by-Cycle
input and output Peak Current Limit, thermal
regulation, thermal shutdown, input UVLO, input
OVP, output OVP etc.
Adjustable Switching Frequency using resistor
Frequency dithering for good EMI performance
Integrated 2-A MOSFET Gate Drivers
Input or Output Average Current Limiting with
stable CC loop
5V/55mA low I
q
LDO to power system MCU
Available in QFN4x4-32 Package
2 Applications
Automotive Start-Stop Systems
Backup Battery and Super capacitor Charging
Industrial PC Power Supplies
USB Power Delivery
3 Description
PL5500 is a synchronous 4-switch bidirectional
Buck-Boost controller capable of regulating the
output voltage at above or below the input voltage.
PL5500 operates over a wide input voltage range of
3.6 V to 32 V (36 V maximum) to support a variety of
applications. PL5500 can operate at charger mode
for 1, 2, 3, 4, 5 and 6 cells battery charge.
PL5500 employs Constant ON time control in buck,
boost and buck-boost operation modes for superior
load and line regulation. The switching frequency
could be set to 150kHz, 300kHz, 600kHz or 1200kHz
based on different resistor value between FREQ pin
and GND pin. The device also features a
programmable soft-start function and offers all kinds
of protection features including cycle-by-cycle current
limiting, input under voltage lockout (UVLO), output
over voltage protection (OVP), input Over Voltage
Protection, thermal shutdown and output short
protection etc.
VADJ, IADJ pins are used to program output VBUS
voltage and output current limit at battery discharging
mode when OTG is high, which makes PL5500 an
excellent option for USB Power Delivery (PD)
application. PL5500 provides voltage control loop,
constant current loop, thermal regulation loop, battery
temperature sensing, which makes it a perfect
solution for batter charge management.
4 Typical Application Schematic
Fig. 1 Application Schematic
VBAT
SW1
SW2
SW1
LG1
HG1
CSN1
CSP1
BST1
BST2
SW2
COMP
VDD
VSET
BRCOM
LDO
IREF
LG2
HG2
CSN2
CSP2
FB2
VBAT
EN
OTG
STAT
VREG
VCC
VBUS
EN
OTG
STAT
VREF
IADJ
I-PWM
VADJ
V-PWM
RCS1
RCS2
CELLS
FREQ
VBUS
TS
TS
33-GND
PL5500
PL5500
DS-PL5500-Rev. 1.0
www.powlicon.com
2 of 18
2018-08-18
© Powlicon Inc.
5 Pin Configuration and Functions
33-GND
PL5500
32
31
COMP
VREF
CELLS
27 26 25
CSN1
EN
VBAT
CSP1
9
10
11 12 13 14 15
FB2
7
6
5
4
IREF
VSET
3
2
1
IADJ
OTG
VADJ
VDD
17
21
22
23
24
LG1
BST1
SW1
SW2
VBUS
2830 29
CSN2
CSP2
LDO
FREQ
STAT
8
18
BST2
TS
HG2
16
HG1
VCC
19
20
LG2
VREG
BRCOM
Fig. 2 Pin-Function (QFN4X4-32)
Pin
Description
Number
Name
1
VADJ
Connect a 0-2V analog voltage or a PWM signal to program voltage reference on VREF pin.
Connect this pin to VDD will force VREF to constant 2V.
2
IADJ
Connect a 0-2V analog voltage or a PWM signal to program voltage reference on IREF pin.
Connect this pin to VDD will force IREF to 2V.
3
VSET
Connect a resistor between VSET and GND to program battery cell type (4.2V, 4.35V, 4.4V,
4.5V) when OTG is low and PL5500 is working in battery charging mode. When OTG is
higher than 1.2V, voltage on VSET pin will be proportional to voltage difference between
CSP2 and CSN2. Application processor can use this information to monitor discharging
current in battery discharging mode.
4
IREF
Reference voltage for input and output current limiting loop.
5
VREF
Voltage reference for voltage control loop
6
BRCOM
Battery internal resistance compensation. The voltage on this pin will be proportional to
voltage difference between CSP1 and CSN1. Application processor can use this information
to monitor charging current in battery charging mode.
7
LDO
Low quiescent current 5V/55mA LDO. Directly powered from VBAT pin. LDO can be used
as power supply for application processor such as MCU. When EN is low, only this LDO will
be active to power MCU and keep low quiescent current for the whole system.
8
STAT
Charging status display when OTG=Low. PGOOD signal when OTG=High.
9
FREQ
Connect to GND to set the switching frequency at 150kHz. Connect this pin to VDD to set
switching frequency at 300kHz. Connect to a resistor divider between VDD and GND to set
frequency to 600k and 1200k Hz.
10
COMP
Error Amplifier output.
11
VREG
Add a resistor divider to program VBUS regulation voltage. When VBUS is pulled down to
be close to VREG setting point due to heavy charging current in battery charging mode, the
VREG regulation loop will take over the control and lower down charging current to keep
VBUS from being further pulled down. VREG is not active in discharging mode.
12
FB2
VBUS voltage feedback. Connect a resistor divider between VBUS and GND to FB2 to
program VBUS voltage in battery discharging mode.
13
CSN2
The minus input of output current sense.
14
CSP2
The positive input of output current sense.
15
VBUS
VBUS voltage
16
HG2
High side MOSFET driver 2.