Application Note
UnitedSiC_AN0016– April 2018
UnitedSiC JFET in Active Mode Applications
Jonathan Dodge, P.E. Active mode
UnitedSiC_AN0016 – April 2018
UnitedSiC JFET in Active Mode Applications
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United Silicon Carbide
1 Introduction
Power MOS devices, which include power MOSFETs of various construction materials and gate structures, as well
as JFETs and IGBTs are three-terminal devices with current flow controlled by the gate. In most power electronic
applications, the gate is driven to either block current flow with the device fully off; or fully on with minimal
conduction loss. The transition between the on and off states generates high heat, and so the transition time is
kept as short as practical to minimize switching power loss. Such is the art of hard-switched switch mode power
supply (SMPS) design.
There are many applications where the switching transition is unavoidably proportionate to the on and off switch
states, or where the operating point is deliberately set within the transition region. This application note
addresses operation of both power MOS and UnitedSiC JFETs in these applications.
2 Operating Region Definitions
The output characteristic of a power MOS or JFET has three regions, cutoff, active, and ohmic, as shown for a
UnitedSiC JFET in Figure 1. In cutoff, the device is considered to be off since only very small current flows. When
the gate-source voltage is driven sufficiently high, the device enters the ohmic region, where the drain-source
voltage v
DS
is small and current flow is largely determined by on-resistance.
Figure 1 Output characteristic of a 1200 V UnitedSiC JFET at 125 °C
The boundary of the ohmic region is defined by:

 


(1)
Between the ohmic and cutoff regions is the active region, designated as such to avoid confusion between
different meanings for linear and saturation regions for power MOS, JFET, and bipolar transistors. Operation
within the active region is therefore designated active mode in this application note, even though in much
literature it is called linear mode. Drain current in active mode depends mostly on gate-source voltage, although
especially at low v
DS
a dependence on drain-source voltage is clearly seen in Figure 1 as well.
The simultaneous current and voltage supported by a device in active mode result in high power that must be
dissipated as heat. Economic functioning in active mode therefore requires full utilization of the forward safe
operating area (FSOA), and understanding device limitations is vital to achieve reliable operation.
Active mode
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UnitedSiC_AN0016 – April 2018
United Silicon Carbide
3 Root Cause of Power MOS Failures in Active Mode
Applications operating in active mode are arguably the most plagued by failures in spite of operating well within
the power MOS datasheet FSOA. The cause of failures is thermal instability, which results in hot spots from
current focusing.
Figure 2 Representation of 5x5 mm power MOS temperature distribution (°C) in [1] clearly showing hot spot phenomenon
Inevitable temperature gradients across a power device chip can lead to hot spots because of a positive change in
current with increasing temperature. A hotter area on the chip focuses more current that causes further heating
and possibly failure from thermal runaway in a localized area. In [1] the effect of thermal instability was shown
graphically by measuring temperatures across a power MOS in active mode. The results are roughly reproduced in
Figure 2, clearly showing a hot spot with a large difference between minimum, maximum, and average
temperatures. The current crowding and the temperature in the hot spot can be very high, resulting in a burn-out
spot and device failure.
In switch-mode applications current crowding is usually not an issue; the active region is traversed very quickly,
and current in the ohmic region of operation is limited by channel and bulk resistances with their corresponding
strong positive temperature dependence. Active mode operation however results in high power dissipation for a
thermally significant length of time. Therefore, thermal instability limits the true safe operating area of a power
device in active mode. Fortunately, many power MOS manufacturers are aware of this and now publish FSOA
curves with a reduction from constant power dissipation lines in the high voltage side of the FSOA. This application
note takes this a step further, and based on the work in [1-3], the actual onset of thermal instability is estimated
based on published datasheet information.
4 Analysis of Thermal Instability of Power MOS in Active Mode
Thermal instability occurs when the electrical power increases more than can be thermally dissipated [4]. With
electrical and thermal power denoted as P
G
and P
θ
respectively, thermal stability is mathematically expressed as:




(2)