Si5332-AM1/2/3 Automotive Grade Device
Reference Manual
The Si5332-AM1/2/3 is a high-performance, low-jitter clock generator capable of synthe-
sizing five independent banks of user-programmable clock frequencies up to 333.33
MHz, while providing up to 12 differential or 24 single-ended output clocks. The Si5332
supports free run operation using an external crystal as well as lock to an external clock
signal. The output drivers are configurable to support common signal formats, such as
LVPECL, LVDS, HCSL, and LVCMOS. Separate output supply pins allow supply voltag-
es of 3.3 V, 2.5 V, 1.8 V and 1.5 V (CMOS only) to power the multi-format output drivers.
The core voltage supply (VDD) accepts 3.3 V, 2.5 V, or 1.8 V and is independent from
the output supplies (VDDOs). Using its two-stage synthesis architecture and patented
high-resolution Multisynth technology, the Si5332 can generate three fully independent/
non-harmonically-related bank frequencies from a single input frequency.
÷ P
PFD LF
÷M
n
/M
d
÷R
÷R
÷R
÷R
÷R
÷R
÷R
÷R
÷R
÷R
÷R
÷R
÷N
0
÷N
1
÷O
0
÷O
1
÷O
2
÷O
3
÷O
4
1-31
10-255
10-50 MHz
2.375-2.625 GHz
10-255
8-255
10-250 MHz
10-250 MHz
10-312.5 MHz
10-312.5 MHz
10-312.5 MHz
10-312.5 MHz
10-312.5 MHz
1-63
10-50 MHz
10-250 MHz
10-250 MHz
10-250 MHz
10-30 MHz
VDD_XTAL
VDDA
VDDOA
VDDOB
VDDOC
VDDOD
VDDOE
XA/CLKIN_1
XB
CLKIN_2
nCLKIN_2
CLKIN_3
nCLKIN_3
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
RELATED DOCUMENTS
• Any-Frequency 6/8/12-output
programmable clock generators
• Offered in three different package sizes,
supporting different combinations of output
clocks and user configurable hardware
input pins
• 32-pin QFN, up to 6 outputs
• 40-pin QFN, up to 8 outputs
• 48-pin QFN, up to 12 outputs (planned
future device)
• Multisynth technology enables any
frequency synthesis on any output up to
250 MHz using N dividers.
• Output frequencies up to 333.33 MHz
using O dividers.
• Highly configurable output path featuring a
cross point mux
• Up to three independent fractional
synthesis output paths
• Up to five independent integer dividers
• Down and center spread spectrum
• Input frequency range:
• External crystal: 16 MHz to 50 MHz
• Differential clock: 10 MHz to 250 MHz
• LVCMOS clock: 10 MHz to 170 MHz
• Output frequency range:
• Differential: 5 MHz to 333.33 MHz
• LVCMOS: 5 MHz to 170 MHz
• User-configurable clock output signal
format per output: LVDS, LVPECL, HCSL,
LVCMOS
• Easy device configuration using our
ClockBuilder Pro™ (CBPro™) software
tool available for download from our web
site
• Temperature range: –40 to +105 °C
• Pb-free, RoHS-6 compliant
• For more information, refer to the Si5332
Automotive Grade Data Sheet
silabs.com
| Building a more connected world. Preliminary Rev. 0.1
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Table of Contents
1. Overview .................................3
2. Power Supply Sequencing ..........................4
3. Input Clocks................................5
3.1 Input Clock Terminations ..........................5
3.1.1 External Crystal ............................5
3.1.2 External Input Clock on XA Input ......................5
3.1.3 External Input Clock on CLKIN_x/CLKIN_x# ..................6
3.2 Calculating Crystal Loading Capacitance .....................8
4. GPIO .................................10
5. Output Clock Terminations .........................11
5.1 DC-Coupled Output Clock Terminations .....................12
5.2 AC-Coupled Output Clock Terminations .....................16
6. Programming the Volatile Memory (Registers) ..................17
6.1 Programming the PLL ...........................18
6.2 Programming the Clock Path .........................21
6.3 Programming the Output Clock Frequency ....................23
6.4 Programming the Output Clock Format ......................25
6.5 Programming for Frequency Select Operations ...................27
6.6 Programming Spread Spectrum ........................28
7. Si5332 Pinout and Package Variant ......................30
8. Recommended Schematic and Layout Practices .................32
9. Register Map ..............................33
10. Revision History............................. 54
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| Building a more connected world. Preliminary Rev. 0.1 | 2