www.infineon.com/coolsic

SILICON CARBIDE

www.power-mag.com Issue 3 2017 Power Electronics Europe

CoolSiC Trench MOSFET

Combining SiC Performance

With Silicon Ruggedness

This article summarizes selected features of the new ColSiC™ MOSFET. The device combines low static and

dynamic losses with high Si-IGBT like gate oxide reliability right fitting to typical industrial requirements. The

temperature behavior, threshold voltage selection and Vgs_on makes the device easy to operate, in

particular for operation in parallel. The switching behavior can be fully controlled by the gate resistor.

Dethard Peters, Thomas Basler, Bernd Zippelius, Thomas Aichinger, Wolfgang Bergner, Romain

Esteve, Daniel Kueck, Ralf Siemieniec, Infineon Technologies AG

SiC MOSFETs based power switches

offer significant system advantages in

terms of power density, efficiency and

cooling effort due to their much lower

losses compared to Si-IGBT. It was shown

that the system costs of solar applications

as well as the running costs of UPS

systems can be drastically reduced [1]

despite the more expensive

semiconductor component. Thus, the

technology is ready to penetrate more and

more applications in the coming years.

Reliability concerns solved

While the electrical performance of the

commercial available SiC devices is already

outstanding, there are still concerns about

the SiC MOSFET reliability [2]. Currently

most of the parts on the market are based

on a planar DMOS like design. In order to

mitigate the very low conductivity of the

planar channel the devices are operated

for full turn on at high gate oxide fields

(using comparably thin gate oxides). Thus,

special care needs to be taken particular

about the potential high field failure rate as

a consequence of the quite high

permanent on state gate oxide stress fields

of above 4 MV/cm [3]. The dilemma

between performance and robustness can

be overcome with the trench concept

introduced by Infineon.

The CoolSiC MOSFET uses a trench

structure showing commonly significantly

higher channel conductivities due to less

defects compared to the planar channel

on the so called Si face of 4H-SiC. An

investigation of different orientations of the

trench sidewalls resulted in slightly

different threshold voltages as well as

significantly different channel mobility as

shown in [4]. In Infineon’s device the most

favorable orientation with respect to the

highest possible channel conductivity was

chosen for the MOS channel.

Figure 1 shows a sketch of the CoolSiC

MOSFET cell. Following the considerations

presented before, the doped regions

adjoining the trench are asymmetric. The

left hand side of the trench sidewall

contains the MOS channel which is aligned

to the so called a-plane of 4H SiC. A large

portion of the bottom of the trench is

embedded into a p-type region which

extends below the bottom of the trench

which also acts a p-type emitter of the

incorporated freewheeling body-diode.

CoolSiC MOSFET structure

This MOSFET structure inherently exhibits a

favorable capacitance ratio. The miller

capacitance CGD is small while CGS is

comparably large. This allows for a well-

controlled switching with very low dynamic

losses [5]. In particular this feature is essential

to suppress undesirable parasitic turn-on.

A decisive criterion to ensure gate oxide

reliability of SiC MOSFETs is the limitation

of the gate oxide field in order to

guarantee a sufficient lifetime and FIT rate.

For SiC trench MOS structures in blocking

state additional care has to be taken since

the electric field in the trench corners is

enhanced due to the trench shape. With

respect to this specific cell configuration

the field peak is found in the left trench

corners. This local maximum of the electric

field determines the lifetime of the gate

oxide in blocking state. Figure 2 presents a

2D simulation result for the electric field

under worst case conditions, i.e. at

maximum drain source voltage of

DSS

= 1200 V and a minimum gate

voltage of V

= -10 V. The simulation

indicates that the electric field in the gate

oxide can be limited to a value sufficiently

low not to conflict with gate oxide lifetime

requirements.

The typical on-resistance for the single

chip device is 45 mΩ at V

=+15 V, I

=20

A and T=25°C. The threshold voltage is

Figure 1: Sketch of a

commonly known

planar-gate MOSFET

(left) and the

CoolSiC™ Trench

MOSFET cell

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