Datasheet

R01DS0261EJ0120 Rev.1.20 Page 1 of 170

Sep 28, 2018

RX230 Group, RX231 Group

Renesas MCUs

Features

■ 32-bit RXv2 CPU core

• Max. operating frequency: 54 MHz

Capable of 88.56 DMIPS in operation at 54 MHz

• Enhanced DSP: 32-bit multiply-accumulate and 16-bit

multiply-subtract instructions supported

• Built-in FPU: 32-bit single-precision floating point (compliant to

IEEE754)

• Divider (fastest instruction execution takes two CPU clock cycles)

• Fast interrupt

• CISC Harvard architecture with 5-stage pipeline

• Variable-length instructions, ultra-compact code

• On-chip debugging circuit

• Memory protection unit (MPU) supported

■ Low power design and architecture

• Operation from a single 1.8-V to 5.5-V supply

• RTC capable of operating on the battery backup power supply

• Three low power consumption modes

• Low power timer (LPT) that operates during the software standby state

■ On-chip flash memory for code

• 128- to 512-Kbyte capacities

• On-board or off-board user programming

• Programmable at 1.8 V

• For instructions and operands

■ On-chip data flash memory

• 8 Kbytes (1,000,000 program/erase cycles (typ.))

• BGO (Background Operation)

■ On-chip SRAM, no wait states

• 32- to 64-Kbyte size capacities

■ Data transfer functions

• DMAC: Incorporates four channels

• DTC: Four transfer modes

■ ELC

• Module operation can be initiated by event signals without using

interrupts.

• Linked operation between modules is possible while the CPU is sleeping.

■ Reset and supply management

• Eight types of reset, including the power-on reset (POR)

• Low voltage detection (LVD) with voltage settings

■ Clock functions

• Main clock oscillator frequency: 1 to 20 MHz

• External clock input frequency: Up to 20 MHz

• Sub-clock oscillator frequency: 32.768 kHz

• PLL circuit input: 4 MHz to 12.5 MHz

• On-chip low- and high-speed oscillators, dedicated on-chip low-speed

oscillator for the IWDT

• USB-dedicated PLL circuit: 4, 6, 8, or 12 MHz

54 MHz can be set for the system clock and 48 MHz for the USB clock

• Generation of a dedicated 32.768-kHz clock for the RTC

• Clock frequency accuracy measurement circuit (CAC)

■ Realtime clock

• Adjustment functions (30 seconds, leap year, and error)

• Calendar count mode or binary count mode selectable

• Time capture function

• Time capture on event-signal input through external pins

■ Independent watchdog timer

• 15-kHz on-chip oscillator produces a dedicated clock signal to drive

IWDT operation.

■ Useful functions for IEC60730 compliance

• Self-diagnostic and disconnection-detection assistance functions for

the A/D converter, clock frequency accuracy measurement circuit,

independent watchdog timer, RAM test assistance functions using the

DOC, etc.

■ External address space

• Four CS areas (4 × 16 Mbytes)

• 8- or 16-bit bus space is selectable per area

■ MPC

• Input/output functions selectable from multiple pins

■ Up to 14 communication functions

• USB 2.0 host/function/On-The-Go (OTG) (one channel),

full-speed = 12 Mbps, low-speed = 1.5 Mbps, isochronous transfer, and

BC (Battery Charger) supported

• CAN (one channel) compliant to ISO11898-1:

Transfer at up to 1 Mbps

• SCI with many useful functions (up to 7 channels)

Asynchronous mode, clock synchronous mode, smart card interface

Reduction of errors in communications using the bit modulation

function

• IrDA interface (one channel, in cooperation with the SCI5)

• I

C bus interface: Transfer at up to 400 kbps, capable of SMBus

operation (one channel)

• RSPI (one channel): Transfer at up to 16 Mbps

• Serial sound interface (one channel)

• SD host interface (optional: one channel) SD memory/ SDIO 1-bit or

4-bit SD bus supported

■ Up to 20 extended-function timers

• 16-bit MTU: input capture, output compare, complementary PWM

output, phase counting mode (six channels)

• 16-bit TPU: input capture, output compare, phase counting mode (six

channels)

• 8-bit TMR (four channels)

• 16-bit compare-match timers (four channels)

■ 12-bit A/D converter

• Capable of conversion within 0.83 μs

• 24 channels

• Sampling time can be set for each channel

• Self-diagnostic function and analog input disconnection detection

assistance function

■ 12-bit D/A converter

• Two channels

■ Capacitive touch sensing unit

• Self-capacitance method: A single pin configures a single key,

supporting up to 24 keys

• Mutual capacitance method: Matrix configuration with 24 pins, supporting

up to 144 keys

■ Analog comparator

• Two channels × two units

■ General I/O ports

• 5-V tolerant, open drain, input pull-up, switching of driving capacity

■ Encryption Functions (TSIP-Lite)

• Unauthorized access to the encryption engine is disabled and

imposture and falsification of information are prevented

• Safe management of keys

• 128- or 256-bit key length of AES for ECB, CBC, GCM, others

• True random number generator

■ Temperature sensor

■ Operating temperature range

•−40 to +85°C

•−40 to +105°C

■ Applications

• General industrial and consumer equipment

PLQP0100KB-B 14 × 14 mm, 0.5 mm pitch

PLQP0064KB-C 10 × 10 mm, 0.5 mm pitch

PLQP0048KB-B 7 × 7 mm, 0.5 mm pitch

PWQN0064KC-A 9 × 9 mm, 0.5 mm pitch

PWQN0048KB-A 7 × 7 mm, 0.5 mm pitch

PTLG0100KA-A 5.5 × 5.5 mm, 0.5 mm pitch

PWLG0064KA-A 5 × 5 mm, 0.5 mm pitch

54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory,

various communication functions including USB 2.0 full-speed host/function/OTG, CAN, SD host

interface, serial sound interface, capacitive touch sensing unit, 12-bit A/D, 12-bit D/A, RTC, Encryption

functions

R01DS0261EJ0120

Rev.1.20

Sep 28, 2018

R01DS0261EJ0120 Rev.1.20 Page 2 of 170

Sep 28, 2018

RX230 Group, RX231 Group 1. Overview

1. Overview

1.1 Outline of Specifications

Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different

packages.

Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will

differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different

Packages.

Table 1.1 Outline of Specifications (1/4)

Classification Module/Function Description

CPU CPU

• Maximum operating frequency: 54 MHz

• 32-bit RX CPU (RX v2)

• Minimum instruction execution time: One instruction per clock cycle

• Address space: 4-Gbyte linear

• Register set

General purpose: Sixteen 32-bit registers

Control: Ten 32-bit registers

Accumulator: Two 72-bit registers

• Basic instructions: 75 (variable-length instruction format)

• Floating-point instructions: 11

• DSP instructions: 23

• Addressing modes: 10

• Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

• On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit

• On-chip divider: 32-bit ÷ 32-bit → 32 bits

• Barrel shifter: 32 bits

• Memory protection unit (MPU)

FPU

• Single precision (32-bit) floating point

• Data types and floating-point exceptions in conformance with the IEEE754 standard

Memory ROM

• Capacity: 128/256/384/512 Kbytes

• Up to 32 MHz: No-wait memory access

32 to 54 MHz: Wait state required. No wait state if the instruction is served by a ROM accelerator hit.

• Programming/erasing method:

Serial programming (asynchronous serial communication/USB communication), self-programming

RAM

• Capacity: 32/64 Kbytes

• 54 MHz, no-wait memory access

E2 DataFlash

• Capacity: 8 Kbytes

• Number of erase/write cycles: 1,000,000 (typ)

MCU operating mode Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled expansion mode

(software switching)

Clock Clock generation circuit

• Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,

PLL frequency synthesizer, USB-dedicated PLL frequency synthesizer, and IWDT-dedicated on-chip

oscillator

• Oscillation stop detection: Available

• Clock frequency accuracy measurement circuit (CAC)

• Independent settings for the system clock (ICLK), peripheral module clock (PCLK), external bus clock

(BCLK), and FlashIF clock (FCLK)

The CPU and system sections such as other bus masters run in synchronization with the system

clock (ICLK): 54 MHz (at max.)

MTU2a runs in synchronization with the PCLKA: 54 MHz (at max.)

The ADCLK for the S12AD runs in synchronization with the PCLKD: 54 MHz (at max.)

Peripheral modules other than MTU2a and S12ADE run in synchronization with the PCLKB: 32 MHz

(at max.)

Devices connected to external buses run in synchronization with the BCLK: 32 MHz (at max.)

The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)

Resets RES# pin reset, power-on reset, voltage monitoring reset, watchdog timer reset, independent watchdog

timer reset, and software reset

Voltage detection Voltage detection circuit

(LVDAb)

• When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt

is generated.

Vol

age detection circuit 0 is capable of selecting the detection voltage from 4 levels

Voltage detection circuit 1 is capable of selecting the detection voltage from 14 levels

Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels