CONTENTS

• General Purpose Clock Generators . . . . 2

• Programmable Clocks . . . . . . . . . . . 3

• Ultra-Low Jitter Clocks . . . . . . . . . . 6

• Low Jitter Clocks . . . . . . . . . . . . . 7

• PCI Express Clocks. . . . . . . . . . . . . 9

• RF Converter Clocks . . . . . . . . . . . 11

IDT clock generation products produce timing signals for use in synchronizing a system’s operation.

At its most basic level, a clock generator consists of a resonant circuit and an amplifier. The resulting

timing signal (or clock signal) can range from a simple 50 percent duty cycle square wave to more

sophisticated arrangements. The resonant circuit is usually a quartz piezo-electric oscillator, although

simpler tank circuits and even RC circuits may be used in some cases.

As the timing output becomes more complex, devices may combine a frequency multiplier, frequency

divider, and frequency mixer operations to produce the desired output signal. Frequency multipliers

and dividers generate an output signal whose output frequency is a harmonic (multiple) of its input

frequency, while the mixer generates sum and difference frequencies. Many devices are also known

as phase-locked loop clocks (PLL clocks), which contain PLLs used to compare the phase of the input

and adjust the frequency of its oscillator to keep the phases matched. Programmable clock genera-

tors allow the multiplier or divider values to be changed, allowing a wide variety of output frequen-

cies to be selected without modifying the hardware.

As the industry-leader in timing solutions, IDT offers a rich portfolio of clock generation devices that

satisfy a variety of performance and programmability requirements. From ultra-low jitter devices that

offer less than 300 femtoseconds of RMS phase jitter over a 12 kHz to 20 MHz integration range, to

highly flexible programmable devices that provide flexibility and performance in a single package.

Clock Generation Overview

IDT

INTEGRATED DEVICE TECHNOLOGY

CLOCK GENERATION 1

The products in this guide

represent just a portion of

the IDT timing portfolio.

For more information about

our comprehensive portfolio

of timing products or to

request samples, please

visit: idt.com/go/timing

849S625i Crystal to LVPECL/LVDS Clock Synthesizer

• Ten selectable differential LVPECL or LVDS outputs

• Output frequencies of 625 MHz, 312.5 MHz, 156.25 MHz or

125 MHz using a 25 MHz crystal

• RMS phase jitter at 156.25 MHz (1 MHz to 20 MHz):

0.375 ps (typical), LVDS outputs

• Cycle-to-cycle jitter: 25 ps (maximum)

• -40°C to 85°C ambient operating temperature

• Available in a 7 x 7 mm 48-TQFP package

Clock Generation

INTEGRATED DEVICE TECHNOLOGY

IDT

CLOCK GENERATION

IDT GENERAL PURPOSE CLOCK GENERATORS are PLL-based products that generate different output frequencies from a common input frequen-

cy. IDT clock generators produce clock output frequencies within strict tolerances to the application they are sourcing. They use a simple, low

cost, fundamental-mode quartz crystal or reference clock as the frequency reference, from which they generate low-jitter output clocks. They

also allow for frequency translation with output frequencies readily selected with very high resolution (very small frequency steps). IDT offers

clock generators with both single ended and differential clock outputs. Many devices provide a programmable-skew feature allowing the user

to adjust the timing of individual outputs. This provides flexibility for last minute clock skew management in the system.

General Purpose Clock Generators

QA[0:5]

nQA[0:5]

NA =

÷1, ÷2,

÷4, ÷5

QB[0:1]

nQB[0:1]

NB =

÷1, ÷2,

÷4, ÷5

QC[0:1]

nQC[0:1]

NC =

÷1, ÷2,

÷4, ÷5

M = ÷25

÷2

VCO

575 MHz - 630 MHz

Phase

Detector

OSC

25 MHz

SEL_OUT

OEA

SELA[1:0]

BYPASS

REF_CLK

OEB

OEC

SELB[0:1]

SELC[0:1]

XTAL_IN

XTAL_OUT

Pulldown

Pullup

Pulldown

Product ID Product Title

Number

of Outputs

Output Type

Output

Freq

Range

(MHz)

Input Freq

(MHz)

Input Type

Core

Voltage

(V)

Output

Voltage

(V)

841602i

FemtoClock

NG Crystal-to-HCSL

Clock Generator

2 HCSL 100, 125 25 Crystal, LVCMOS 3.3 3.3

841604i-01

FemtoClock NG Crystal-to-HCSL

Clock Generator

4 HCSL 100, 125 25 Crystal, LVCMOS 3.3 3.3

841608i

FemtoClock NG Crystal-to-HCSL

Clock Generator

8 HCSL 100, 125 25 Crystal, LVCMOS 3.3 3.3

849S625i

Crystal-to-LVPECL/LVDS

Clock Synthesizer

10 LVDS, LVPECL

125,

156.25,

312.5, 625

25 Crystal, LVCMOS 3.3 3.3

8V44N4614

FemtoClock NG Jitter Attenuator

and Clock Synthesizer

LVDS, LVPECL,

LVCMOS

25, 100,

125, 156

25, 50, 100,

200

Crystal, LVCMOS,

LVDS, LVPECL

3.3 3.3

8413S12Bi HCSL/LVCMOS Clock Generator 14 LVCMOS, HCSL

100, 125,

156.25,

312.5

Crystal, LVCMOS,

LVTTL

3.3 2.5, 3.3

Clock Generation

IDT

INTEGRATED DEVICE TECHNOLOGY CLOCK GENERATION

PROGRAMMABLE CLOCK GENERATORS allow designers to save board space and cost by replacing crystals, oscillators (including program-

mable oscillators), and buffers with a single timing device, making them well-suited for consumer, data communications, telecommunications

and networking applications. These devices are often referred to as programmable clock generators, or programmable PLL clock generators.

Among others, IDT programmable clock generator families include third-generation Universal Frequency Translators (UFT™), FemtoClock

NG,

and VersaClock 5, each providing a different level of jitter performance, power consumption, flexibility, and cost.

THE UFT FAMILY of programmable timing devices is optimized for high-performance optical networks, wireless base stations, and 10 / 40 /

100 GbE applications. These devices are the industry’s first single-chip programmable solutions capable of generating eight different output

frequencies with less than 300 femtoseconds RMS phase jitter over the standard 12 kHz to 20 MHz integration range. The third-generation UFT

family of timing devices offers eight independently-programmable clocking outputs with the flexibility to apply virtually any input frequency and

select virtually any output frequency.

IDT FEMTOCLOCK NEXT GENERATION (NG) devices are stand-alone programmable clock generators that replace crystal and SAW oscillators

in high-performance applications. Employing a simple, low-cost, fundamental-mode quartz crystal as the low frequency reference these devices

synthesize high-quality, low-jitter clock signals with < 300 fs of RMS phase jitter, up to 1.3 GHz. In addition, this family offers significant power

savings, and is optimized for 10 Gigabit Ethernet, PCI Express

, Fibre Channel and SONET.

VERSACLOCK

DEVICES are in-system programmable clock generators featuring universal output pairs capable of producing independent

frequencies up to 350 MHz as HCSL, LVPECL, LVDS, or dual LVCMOS outputs. With RMS phase jitter of < 500 fs for VersaClock 6 and <700 fs for

VersaClock 5, this family meets the stringent jitter requirements of PCI Express Gen 1/2/3, USB 3.0, and 1G/10G Ethernet. The high-performance

clock generator operates at less than 100 mW core power (50 percent lower than competing devices), helping to ease system thermal con-

straints, reduce operating power expenses, and maximize battery life.

Programmable Clocks

Continued next page

5P49V5901 VersaClock 5 Low Power Programmable Clock

• High performance, low phase noise PLL, <0.7 ps RMS typical

phase jitter on outputs:

– PCIe Gen 1/2/3 compliant clock capability

– USB 3.0 compliant clock capability

– Gigabit Ethernet clock capability (1GbE, 10GbE)

• Generates up to four independent output frequencies

with four Fractional Output Dividers (FODs)

• Four banks of internal non-volatile in-system programmable

or factory programmable OTP EPROM

• 4 x 4 mm 24-VFQFPN package

FOD1

OUT1

OUT1B

DDO

OUT0_SEL_I

DDO

FOD2

OUT2

OUT2B

FOD3

OUT3

OUT3B

FOD4

OUT4

OUT4B

PLL

OTP

and

Control

Logic

SD/OE

SEL1/SDA

SELO/SCL

DDA

DDD

CLKIN

CLKINB

CLKSEL

XIN/REF

XOUT

8T49N286 FemtoClock NG Universal Frequency Translator

(4-in / 2-PLL / 8-out)

• Compliant with Telcordia GR-253-CORE (SONET) & ITU-T

G.813/G.8262 (SDH/SONET & SyncE) when paired with a

Synchronous Equipment Timing Source (SETS ) device

• 8 LVPECL, LVDS, HCSL or 16 LVCMOS output clocks ranging from

8 kHz up to 1.0 GHz (diff), 8 kHz to 250 MHz (LVCMOS)

• 10 x 10 mm 72-VFQVN package

IntN

IntN Output

Divider

IntN Output

Divider

FracN Output

Divider

FracN Output

Divider

XTAL

CLK0

OSC

CLK1

CLK2

CLK3

Status Registers

GPIO

Logic

GPIO nINT PLL_BYPS_A0/nCS, S_A1/SDInWP

Control Registers

C/SPI Slave

OTP

LOS

C Master

Serial (I

C) EEPROM

Reset

Logic

Fractional

Feedback

APLL 1

Fractional

Feedback

APLL 1

Holdover 1

Lock 1

Holdover 0

Lock 0

Input Clock

Monitoring,

Priority, &

Selection

SCLK/SCLK

SDATA/SDO

nRST