XAPP1290 (v1.2) October 2, 2017 1

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Summary

This application note describes a module containing control logic to couple the Xilinx

SMPTE

SD/HD/3G-SDI LogiCORE™ IP core with the Kintex

UltraScale™ GTH transceivers to form a

complete SDI interface. An example SDI design that runs on the Xilinx KCU105 evaluation board

is also provided.

Reference Design

The Society of Motion Picture and Television Engineers (SMPTE) serial digital interface (SDI)

standards are widely used in professional broadcast video equipment. SDI interfaces are used in

broadcast studios and video production centers to carry uncompressed digital video, along

with embedded ancillary data such as multiple audio channels.

The SMPTE SD/HD/3G-SDI LogiCORE IP core (SDI core) is a generic SDI receive/transmit

datapath that does not have any device-specific control functions. It can be connected to a GTH

transceiver to implement an SDI interface capable of supporting the SMPTE SD-SDI, HD-SDI

and 3G-SDI standards. The SDI core and GTH transceiver must be supplemented with some

additional logic to connect them and implement a fully functional SDI interface. This

application note describes the additional control and interface logic and a reference design

(example SDI design). This document uses the term SDI to refer to the SMPTE interface

standards including SD-SDI, HD-SDI and 3G-SDI. Additional information for these interfaces is

available from SMPTE [Ref 1].

Kintex UltraScale GTH transceivers can support all SDI bit rates up to, and including, 3G-SDI.

The maximum line rates supported by GTH transceivers for each combination of speed grade

and device package are described in Kintex UltraScale FPGAs Data Sheet: DC and AC Switching

Characteristics (DS892) [Ref 2].

Hardware

The primary functions of the device-specific control logic are:

• Reset logic for GTH transceivers

• Dynamic switching of the RX and TX serial clock dividers to support SD-SDI, HD-SDI and

3G-SDI

Application Note: Kintex UltraScale FPGAs

XAPP1290 (v1.2)

October 2, 2017

Implementing SMPTE 3G-SDI Interfaces

with Kintex UltraScale GTH Transceivers

Authors: Jerin Jacob, Gilbert Magnaye

Reference Design

XAPP1290 (v1.2) October 2, 2017 2

www.xilinx.com

• Dynamic TX reference clock switching to support two different bit rates in each of the

HD-SDI and 3G-SDI standards:

1.485 Gb/s and 1.485/1.001 Gb/s in HD-SDI mode

2.97 Gb/s and 2.97/1.001 Gb/s in 3G-SDI mode

• Data recovery unit for recovering data in SD-SDI mode

• RX bit-rate detection to determine if the receiver is receiving integer frame-rate signals

(line rates such as 1.485 Gb/s and 2.97 Gb/s) or fractional frame-rate signals (line rates such

as 1.485/1.001 Gb/s and 2.97/1.001 Gb/s)

To simplify the process of creating an SDI interface, the example SDI design supplies a wrapper

file that contains an instance of the control module for the GTH transceiver, one GTH transceiver

channel instance, and the SDI core with the necessary connections between them.

The IP cores and modules used in the example SDI design are listed here. Xilinx IP cores are

available in the Vivado Design Suite IP catalog:

• The SDI core refers to the SMPTE SD/HD/3G-SDI LogiCORE IP that is available in the Vivado

IP catalog. The SDI core implements SMPTE SD-SDI, HD-SDI and 3G-SDI standards. See the

SMPTE SMPTE SD/HD/3G-SDI 3.0 LogiCORE IP Product Guide (PG071) [Ref 3] for reference

information.

• The control module implements the various device-specific functions required when using

the GTH transceiver and the SDI core to implement an SDI interface. The control module is

supplied as source code with the example SDI design.

• The UltraScale FPGAs Transceivers Wizard IP core generates a GTH transceiver wrapper that

includes an instance of a single GTHE3_CHANNEL primitive and a corresponding control

module. See UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182)

[Ref 4] for reference information.

• The SDI wrapper instantiates and interconnects the SDI core, GTH wizard IP core, and the

control module. The SDI wrapper is supplied as source code with the example SDI design.

• The SDI wrapper support module contains one SDI wrapper instance and a

GTHE3_COMMON primitive for a GTH Quad. This wrapper is instantiated once per Quad.

The associated QPLL clock, reference clock, and lock outputs should be connected to the

SDI wrapper residing in the same Quad but in a different channel. If the QPLL is not used in

the SDI application, this wrapper is not required.