FN7841 Rev 3.00 Page 1 of 16
September 30, 2016
FN7841
Rev 3.00
September 30, 2016
ISL80111, ISL80112, ISL80113
Ultra Low Dropout 1A, 2A, 3A Low Input Voltage NMOS LDOs
DATASHEET
The ISL80111, ISL80112, and ISL80113 are ultra low dropout
LDOs providing the optimum balance between performance, size
and power consumption in size constrained designs for data
communication, computing, storage and medical applications.
These LDOs are specified for 1A, 2A and 3A of output current and
are optimized for low voltage conversions. Operating with a V
IN
of
1V to 3.6V and with a legacy 2.9V to 5.5V on the BIAS, the V
OUT
is
adjustable from 0.8V to 3.3V. With a V
IN
PSRR greater than 40dB
at 100kHz makes these LDOs an ideal choice in noise sensitive
applications. The guaranteed ±1.6% V
OUT
accuracy overall
conditions lend these parts to supplying an accurate voltage to
the latest low voltage digital ICs.
An enable input allows the part to be placed into a low quiescent
current shutdown mode. A submicron CMOS process is utilized for
this product family to deliver best-in-class analog performance
and overall value for applications in need of input voltage
conversions typically below 2.5V. It also has the superior load
transient regulation unique to a NMOS power stage. These LDOs
consume significantly lower quiescent current as a function of
load compared to bipolar LDOs.
Features
• Ultra low dropout: 75mV at 3A, (typical)
• Excellent V
IN
PSRR: 70dB at 1kHz (typical)
• ±1.6% guaranteed V
OUT
accuracy for -40ºC < T
J
< +125ºC
• Very fast load transient response
• Extensive protection and reporting features
•V
IN
range: 1V to 3.6V, V
OUT
range: 0.8V to 3.3V
• Small 10 Ld 3x3 DFN package
Applications
• Noise-sensitive instrumentation and medical systems
• Data acquisition and data communication systems
• Storage, telecommunications and server equipment
• Low voltage DSP, FPGA and ASIC core power supplies
• Post-regulation of switched mode power supplies
Related Literature
��� UG009, “ISL8011xEVAL1Z Evaluation Board User Guide”
FIGURE 1. TYPICAL APPLICATION SCHEMATIC FIGURE 2. DROPOUT VOLTAGE OVER-TEMP AND I
OUT
FIGURE 3. V
IN
PSRR vs LOAD CURRENT (ISL80113)
FIGURE 4. V
ADJ
vs TEMPERATURE
VIN
9
VIN
10
ENABLE
7
VBIAS
4
GND
1.2V ±5%
C
IN
10µF
VIN
C
BIAS
5
PG
6
VOUT
1
VOUT
2
VOUT
1.0V
C
OUT
10µF
ADJ
3
PGOOD
R
4
1.0kΩ
R
3
1.0kΩ
EN
OPEN-DRAIN COMPATIBLE
3.3V ±10%
VBIAS
1µF
ISL80111, ISL80112, ISL80113
TEMPERATURE (
°
C)
0
10
20
30
40
50
60
70
80
90
100
-40 25 85 125
DROPOUT VOLTAGE, BIAS = 5V (mV)
3A
2A
1A
0
20
40
60
80
100
100 1k 10k 100k 1M
PSRR (dB)
FREQUENCY (Hz)
I
OUT
= 2A
I
OUT
= 3A
I
OUT
= 0A
I
OUT
= 1A
BIAS = 5V
V
OUT
= 2.5V
V
IN
= 3.3V
C
OUT
= 10µF
0.985
0.990
0.995
1.000
1.005
1.010
1.015
-40 0 25 85 125
TEMPERATURE (°C)
V
ADJ
+25°C NORMALIZED
ISL80111, ISL80112, ISL80113
FN7841 Rev 3.00 Page 2 of 16
September 30, 2016
Block Diagram
Pin Configuration
ISL80111, ISL80112, ISL80113
(10 LD 3X3 DFN)
TOP VIEW
R7
EN
EN
ENEN
ENABLE
M7
500mV
425mV
M3
POWER NMOS
M1
VIN
VOUT
GND
PG
ADJ
M
2
+
-
+
-
+
-
+
-
+
-
IL/10,000
IL
VBIAS
CURRENT
LIMIT
DRIVER
BIAS
EN
THERMAL
SHUTDOWN
UVLO
VIN
UVLO
VIN
FIGURE 5. BLOCK DIAGRAM
2
3
4
1
5
9
8
7
10
6
VOUT
VOUT
ADJ
VBIAS
GND
VIN
VIN
NC
ENABLE
PG
EPAD
(GND)
Pin Descriptions
PIN
NUMBER PIN NAME DESCRIPTION
1, 2 VOUT Output voltage pin. Range 0.8V to 3.3V
3 ADJ ADJ pin for externally setting V
OUT
.
4 VBIAS Bias voltage pin for internal control circuits.
Range 2.9V to 5.5V
5GNDGround pin
6PGV
OUT
in regulation signal. Logic low defines
when V
OUT
is not in regulation. Range 0V to
BIAS
7ENABLE V
IN
independent chip enable. TTL and CMOS
compatible. Range 0V to V
BIAS.
V
EN
must
always be less than or equal to the voltage
applied to VBIAS. When this pin is not used, it
must be tied to VBIAS.
8 NC No Connect
9, 10 VIN Input supply pins. Range 1.0V to 3.6V
EPAD EPAD at ground potential. It is recommended
to solder the EPAD to the ground plane.