PRODUCT
PREVIEW
DIGITAL PLL ZL30108
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The ZL30108 is the world’s smallest digital phase locked loop (DPLL) for
SONET/SDH line cards in high-speed networking equipment.
Measuring just 5 mm x 5 mm, the device provides high-performance line card
synchronization that surpasses all OC-3/STM-1 speci cations. With integrat-
ed features, including reference monitoring, reference switching, automatic
holdover, jitter ltering and jitter shaping, the DPLL ensures reliable line card
clocks even in the presence of jitter, wander and interruptions to the reference
signals.
The ZL30108 can be used in combination with Zarlink’s family of analog PLLs
to provide an easy-to-implement, compact timing and synchronization solu-
tion for high-speed SONET/SDH network equipment.
High Performance/Small Package
Small 5 mm x 5 mm package
addresses dense SONET/SDH line
card “real estate” constraints
Jitter performance better than
24 psrms on 19.44 MHz clock,
allowing a direct interface to
OC-3/STM-1 framers and mappers
Accepts two input references,
synchronizing to 2 kHz, 8 kHz,
1.544 MHz, 2.048 MHz, 8.192
MHz, 16.384 MHz and 19.44 MHz
frequencies
Automatic reference frequency
detection with reference out-of-
range detectors continuously
monitor timing references and raise
an alarm if frequency error exceeds
user-de ned limits
Accurate holdover ensures precise
timing if the network reference is
temporarily lost
Innovative jitter shaping and ltering
techniques ensure compatibility
with Zarlink analog PLLs for higher-
speed timing and synchronization
Simplifi es Design of Line Cards
Supports free-run and normal
(locked) modes
Automatic entry into Holdover and
return from Holdover
Simpli ed control via hardware
interface pins to operate the device
without the need for a dedicated
microprocessor interface
External oscillator/crystal enhances
exibility, offering designers choice
of size, source, quality, cost
Standards Compliant
ITU-T G.813 STM-1 jitter
performance
Telcordia GR-253-CORE OC-3 jitter
performance
Customer Support
The ZL30108 is supported by a cus-
tomer evaluation board and Zarlink’s
network of in-house eld application
and design engineers.
Applications
Line card synchronization for
SONET and SDH systems
Wireless base station network
interface cards
Packaging and Availability
Ultra-compact (5 mm x 5 mm)
32-pin QFN package
Available now in production
quantities
APPLICATION
ZL30108 DIGITAL PLL
www.ZARLINK.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries is believed to be reliable.
The products, their specifi cations, services and other information appearing in this publication are subject to change by Zarlink without notice.
ZARLINK, ZL, and the Zarlink logo are trademarks of Zarlink Semiconductor Inc.
© 2004, Zarlink Semiconductor Inc. All Rights Reserved. Publication Number PP5897
SONET/SDH Timing Distribution via Backplane
Secondary Ref. Clock
Primary Ref. Clock
Input Frequencies
2, 8 kHz, 1.544, 2.048,
8.192, 16.384 or 19.44 MHz
Secondary Ref. Clock
Primary Ref. Clock
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ZL30414/6 (OC-192/STM-64)
ZL30406 (OC-48/STM-16)
ZL30415 (OC-12/STM-4)
Accurate References Monitoring
Fail and lock detection with
Automatic holdover entry/exit
*
Ultra-Low Jitter
Output
Frequencies
19.44, 38.88,
77.76, 155.52,
or 622.08 MHz
19.44 MHz Clock
8 kHz
Framing Pulse
2 kHz
Multi-frame Pulse
SONET/SDH
Network Interface
DPLL
ZL30108
SONET/SDH
Clock
Multiplier
APLL*
20 MHz
Osc./xtal
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Simple Hardware Control Interface (4 pins)
Mode Select, Reference Select,
Out-Of-Range Selection, TIE Circuit Reset
19.44 MHz Clock
Low Intrinsec Jitter
compliant with
GR-253 OC-3 and
G.813 STM-1
specifications
8 kHz
Framing Pulse
2 kHz
Multi-frame Pulse
SONET/SDH
Network Interface
DPLL
ZL30108
STM-1/OC-3
Framer,
Mapper
SERDES
20 MHz
Osc./xtal
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Redundant Card
SONET/SDH
Network
Element DPLL
ZL30407
Clock Control &
Monitoring
20 MHz
Osc.
SONET and SDH are the leading transport technologies for
high-speed networks, offering versatility, reliability and the
ability to support synchronous and asynchronous traf c.
Zarlink’s ZL30108 DPLL provides the best combination of
features, jitter performance and small size for SONET/SDH
line cards operating at rates up to OC-3/STM-1. The device
can also be used in combination with Zarlink’s family of ana-
log PLLs to provide end-to-end timing and synchronization
for higher-speed networking equipment.
As illustrated below, the ZL30108 accepts a primary and
secondary input reference synchronized to a wide range of
frequencies. Each input is continuously monitored for fre-
quency accuracy and pulse quality.
When the network frequencies are outside the program-
mable frequency range, the ZL30108 provides hitless refer-
ence switching between the primary and secondary clock
without any phase disruption to the line card clocks and
frame pulses.
The ZL30108 provides a 19.44 MHz clock output with jitter
performance of better than 24 psrms, delivering signi cant
jitter margin versus OC-3/STM-1 speci cations. The device
also produces an 8 kHz framing pulse and 2 kHz multi-frame
pulse with less than 0.5 nspp.
With the rollout of increasingly complex, high-speed network
architectures, designers must use combinations of digital
and analog PLLs working in tandem. With innovative tech-
niques, jitter from the ZL30108 can be shaped so it produces
lower jitter, or is easily ltered by a Zarlink analog PLL for
higher frequency applications.
For example, the ZL30108 DPLL and ZL30415 analog PLL
can be used in tandem to provide and end-to-end, extremely
compact and easy-to-implement timing and synchronization
solution for OC-12/STM-4 line cards.
SONET/SDH Line Card Timing