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ZL30108
DIGITAL PHASE-LOCKED LOOP (DPLL)
• Small 5 mm x 5 mm package addresses
dense SONET/SDHline card “real estate”
constraints
• Jitterperformancebetterthan24psrmson
19.44MHzclock,allowingadirectinterface
toOC-3/STM-1framersandmappers
• Acceptstwoinputreferences,synchronizing
to2kHz,8kHz,1.544MHz,2.048MHz,
8.192 MHz, 16.384 MHz and 19.44 MHz
frequencies
• Automatic reference frequency detection
with reference out-ofrange detectors
continuouslymonitortimingreferencesand
raise an alarm if frequency error exceeds
user-definedlimits
• Accurate holdover ensures precise timing
ifthenetworkreferenceistemporarilylost
• Innovative jitter shaping and filtering
techniques ensure compatibility with
Microsemi analog PLLs for higherspeed
timingandsynchronization
The ZL30108 is the world’s smallest digital phase-locked loop (DPLL) for SONET/
SDH line cards in high-speed networking equipment.
Measuring just 5 mm x 5 mm, the device provides high-performance line card
synchronization that surpasses all OC-3/STM-1 specifications. With integrated
features, including reference monitoring, reference switching, automatic holdover,
jitter filtering and jitter shaping, the DPLL ensures reliable line card clocks even in the
presence of jitter, wander, and interruptions to the reference signals.
The ZL30108 can be used in combination with Microsemi
®
family of analog PLLs to
provide an easy-to-implement, compact timing and synchronization solution for high-
speed SONET/SDH network equipment.
Customer Support
The ZL30108 is supported by a customer
evaluationboardandthenetworkofin-house
field application and design engineers of
Microsemi.
Applications
• Line card synchronization for SONET and
SDHsystems
• Wireless base station network interface
cards
Packaging and Availability
• Ultra-compact (5 mm x 5 mm) 32-pin
QFNpackage
• Availablenowinproductionquantities
Standards Compliant
• ITU-TG.813STM-1jitterperformance
• Telcordia GR-253-CORE OC-3 jitter
performance
ZL30108 Simplified Block Diagram
SONET/SDH
Network Interface DPLL
Independent
Input References
Digital PLL
SONET/SDH
Low Jitter
Clock and Frame
Pulse Outputs
Reference Switching
with Phase Transient
Suppression
Jitter and Wander
Filtering
Automatic High
Accuracy Holdover
(0.01 ppm)
Hardware Control and Monitoring
Manual Reference Switching
Reference Monitoring with selectable out of range frequency limits
Primary
Reference
2, 8 kHz, 1.5, 2,
8, 16 or 19 MHz
Secondary
Reference
2, 8 kHz, 1.5, 2,
8, 16 or 19 MHz
19.44 MHz
Clock
2 kHz
Frame Pulse
Clock
Outputs
20 MHz
Osc./xtal
Simple Control and Monitoring
Clock
Inputs
8 kHz
Frame Pulse
High Performance/Small Package
Simplifies Design of Line Cards
• Supports free-run and normal (locked)
modes
• Automatic entry into Holdover and return
fromHoldover
• Simplified control via hardware interface
pinstooperatethedevicewithouttheneed
foradedicatedmicroprocessorinterface
• External oscillator/crystal enhances
flexibility,offeringdesignerschoiceof size,
source,quality,��cost
Microsemi Corporate Headquarters
OneEnterprise,AlisoViejoCA92656USA
WithintheUSA:
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Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete
subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com.
ZL30108
©2012MicrosemiCorporation.Allrightsreserved.MicrosemiandtheMicrosemilogoaretrademarksofMicrosemiCorporation.Allothertrademarksand
servicemarksarethepropertyoftheirrespectiveowners.
PublicationNumber:PP5897
SONET and SDH are the leading transport technologies for high-
speed networks, offering versatility, reliability, and the ability to support
synchronousandasynchronoustraffic.
Microsemi ZL30108 DPLL provides the best combination of features,
jitterperformanceandsmallsizeforSONET/SDHlinecardsoperatingat
rates up to OC-3/STM-1. Thedevice can alsobe used in combination
withMicrosemifamily of analogPLLsto provideend-to-end timing and
synchronizationforhigher-speednetworkingequipment.
Asillustratedbelow,theZL30108acceptsaprimaryandsecondaryinput
reference synchronized to a wide range of frequencies. Each input is
continuouslymonitoredforfrequencyaccuracyandpulsequality.
Whenthenetworkfrequenciesareoutsidetheprogrammablefrequency
range, the ZL30108 provides hitless reference switching between the
primaryandsecondaryclockwithoutanyphasedisruptiontothelinecard
clocksandframepulses.
TheZL30108providesa19.44MHzclockoutputwithjitterperformance
ofbetterthan24 psrms,deliveringsignificantjittermarginversusOC-3/
STM-1specifications.Thedevicealsoproducesan8kHzframingpulse
and2kHzmulti-framepulsewithlessthan0.5nspp.
Withtherolloutofincreasinglycomplex,high-speednetworkarchitectures,
designers must use combinations of digital and analog PLLs working
in tandem. With innovative techniques, jitter from the ZL30108 can be
shaped so it produces lower jitter, or is easily filtered by a Microsemi
analogPLLforhigherfrequencyapplications.
Forexample,theZL30108DPLLandZL30415analogPLLcanbeused
in tandem toprovideand end-to-end, extremelycompact and easy-to-
implement timing and synchronization solution for OC-12/STM-4 line
cards.
Digital Phase-Locked Loop (DPLL)
SONET/SDH Line Card Timing
Accurate References Monitoring
Fail and lock detection with
Automatic holdover entry/exit
Redundant Card
SONET/SDH
Timing Card
SONET/SDH Line Cards (up to OC-192/STM-64)
SONET/SDH and PDH Line Cards (up to OC-3/STM-1)
CLock Control and
Monitoring
20 MHz
Osc.
ZL30407
ZL30108
SONET/SDH
Network
Element DPLL
SONET/SDH
Network Interface
DPLL
SONET/SDH
Clock
Multiplier
APLL*
20 MHz
Osc./xtal
20 MHz
Osc.
ZL30106
SONET/SDH
Network Interface
DPLL
Primary Reference Clock
Secondary Reference Clock
19.44 MHz Clock
Input Frequencies
2, 8 kHz, 1.544, 2.048,
8.192, 16.384 or 19 MHz
8 kHz
Framing Pulse
2 kHz
Multi-frame Pulse
Ultra-Low Jitter
Output
Frequencies
19.44, 38.88,
77.76, 155.52,
or 622.08 MHz
* ZL30414/6 (OC-192/STM-64)
ZL30406 (OC-48/STM-16)
ZL30415 (OC-12/STM-4)
SONET/SDH Timing Distribution via Backplane
Primary Reference Clock
Secondary Reference Clock
Simple Hardware Control Interface (4 pins)
Mode Select, Reference Select,
Out-Of-Range Selection, TIE Circuit Reset
20 MHz
Osc./xtal
STM-1/OC-3
Framer,
Mapper
SERDES
19.44 MHz Clock
Low Intrinsec Jitter
compliant with
GR-253 OC-3 and
G.813 STM-1
specifications
8 kHz
Framing Pulse
2 kHz
Multi-frame Pulse