PRODUCT

PREVIEW

SONET/SDH LINE CARD SYNCHRONIZER

ZL30117/22

Reference

Clocks

2 kHz

N x 8 kHz

Frame

Pulse

166.67 Hz

400 Hz

1 kHz

2 kHz

8 kHz

64 kHz

Controller

and

State

Machine

Input

Monitors

Master

Clock

SONET /SDH

622.08 MHz

155.52 MHz

77.76 MHz

19.44 MHz

etc...

Programmable

Synthesizer

2 kHz

N x 8 kHz

Line Card

Synchronizer

Input

References

Clock Inputs

Frame Pulse

Inputs

Serial

Peripheral

Interface

20 MHz

Osc

Clock and

Frame Pulse

Outputs

Clock and

Frame Pulse

Outputs

Digital

PLL

Output

Synthesizers

ZL30117 Simpliﬁed Block Diagram

Zarlink’s ZL30117 and ZL30122 chips are the industry’s smallest, low-

est power programmable analog/digital PLLs that solve the timing

challenges posed by the popular AdvancedTCA (telecommunications

computing architecture), AMC (advanced mezzanine card) and MicroTCA

architectures.

Highly integrated devices, the ZL30117/22 PLLs combine the hitless ref-

erence switching capabilities of a digital PLL with the jitter performance

of an analog PLL. The ZL30117 and ZL30122 are pin compatible and

software compatible devices differentiated by jitter performance. With

ultra-low jitter performance of less than 1ps, the ZL30117 can be used

in applications up to OC-192/STM-64. The ZL30122 limits jitter to less

than 3ps and can be used for applications up to OC-12/STM-16. The

ZL30117/22 devices accept three reference inputs, supporting clock

frequencies in any multiple of 8 kHz up to 77.76 MHz, as well as support-

ing 2 kHz. The ZL30117/22 can directly lock to any of the three standard

clock inputs available to an AMC in an ATCA or MicroTCA application.

The holdover capability of the ZL30117/22 chips also enables them to

ride out a complete loss of an incoming reference, which can occur when

switching from a failed clock unit to a backup clock unit. The ZL30117/22

PLLs continue to operate in full compliance with network requirements

for several seconds after losing their reference, allowing time for the sys-

tem to switch to another reference source.

Simplifying design, the device synthesizes SONET/SDH interface clocks,

tributary clock families and SBI or Telecom busses without requiring

signicant board space or the use of multiple PLLs.

Integrated Timing Chips for SONET/

SDH Line Cards

Pin compatible and software

compatible single-chip devices

integrate reference switching

performance of a DPLL with jitter

generation of an APLL

• ZL30117 meets jitter

requirements up to OC-192/STM-64

• ZL30122 meets jitter

requirements up to OC-12/STM-16

Congurable DPLL

•

Provides all features for generating

SONET/SDH compliant clocks

PLL operates in free-run, normal

and holdover modes and provides

automatic hitless reference

switching

CMOS outputs for 19.44 MHz and

77.76 MHz clocks eliminate external

dividers or clock multiplying PLLs

Programmable frame pulse

formatter replaces CPLD or FPGA

gates

Selectable output clocks (6.48

MHz, 19.44 MHz, 38.88 MHz, 51.84

MHz, 77.76 MHz, 155.52 MHz,

311.04 MHz, 622.08 MHz) eliminate

external dividers & clock multiplying

DPLLs

Programmable output synthesizers

generate clock frequencies from

any multiple of 8 kHz up to 77.76

MHz and 2 kHz

Three reference inputs supporting

clock frequencies in any multiple of

8 kHz up to 77.76 MHz and 2 kHz

Meets Telcordia GR-253-CORE and

ITU-T G.813 jitter requirements up

to OC-192/STM-64

Customer Support

The ZL30117 and ZL30122 chips

are supported by evaluation boards,

reference designs and Zarlink’s

network of in-house eld application

and design engineers.

Applications

WAN router line cards

DSLAM line cards

RNC/Mobile switching center line

cards

Next generation SONET/SDH line

cards

AdvancedTCA™ boards

Advanced Mezzanine Cards

ZL30117/22 Simpliﬁed Block Diagram

APPLICATION

ZL30117/22

SONET/SDH LINE CARD SYNCHRONIZER

w w w . Z A R L I N K . c o m

Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries is believed to be reliable.

The products, their speciﬁcations, services and other information appearing in this publication are subject to change by Zarlink without notice.

ZARLINK, ZL, ZLE and the Zarlink logo are trademarks of Zarlink Semiconductor Inc. AdvancedTCA is a trademark of PCI Industrial Computer

Manufacturers Group.

20 MHz

OCXO/

TCXO

System

Clock

Timing

Cards

Clock

Selection

Circuitry

ATCA Carrier Board

Advanced

Mezzanine

Card

ZL30121

ATCA Backplane Clocks

Input reference timing distribution bus via backplane

ZL30117

OC-48/STM-16

Framer/Mapper

/SERDES

20 MHz

XTAL/XO

20 MHz

XTAL/XO

CLK3

CLK3 CLK3

CLK2

CLK1

Advanced

Mezzanine

Card

ZL30122

OC-12/STM-4

Framer/Mapper

/SERDES

CLK3

CLK2

CLK1

Zarlink’s ZL30117 and ZL30122 are compact, highly inte-

grated PLLs that synthesize SONET/SDH interface clocks,

tributary clock families and SBI or Telecom bus clocks

locked to backplane references. Incorporating digital and

analog PLLs, these single chip devices manage timing for

next-generation SONET/SDH platforms operating at speeds

up to OC-192/STM-64. The ZL30117 and ZL30122 are pin

compatible and software compatible devices differentiated

by jitter performance. With ultra-low jitter performance of

less than 1ps, the ZL30117 can be used in applications up

to OC-192/STM-64. The ZL30122 limits jitter to less than

3ps and can be used for applications up to OC-12/STM-16.

Competing two-chip or module approaches are more than

twice the size of the ZL30117/22 and require external de-

vices to manage high-speed network timing.

As illustrated below the ZL30117/22 can lock to any of the

CLK1, CLK2 or CLK3 AMC (advanced mezzanine card) clock

signals. When the ACTA carrier board switches its timing

source between the redundant ATCA backplane clocks, the

clock selection circuitry needs only to squelch its clock out-

puts to force the ZL30117/22 into holdover and then switch

over to the new clock source. The ZL30117/22 prevents

bit errors during the switch-over by continuing to generate

stable clocks.

The ZL30117/22 can be congured to manually or automati-

cally switch between valid input references upon reference

failure. When using automatic reference switching, reference

selection criteria is based on input priority and an optional

revertive feature ensures the highest priority valid reference

is always selected. When no valid references are available,

the device automatically enters holdover mode and contin-

ues to generate output clocks based on historical reference

frequency data.

The ZL30117/22 can simultaneously generate ve output

clocks from two independent clock frequency families. Com-

mon SONET/SDH clock frequencies, programmable n x 8

kHz clock frequencies and a variety of programmable frame

pulses can be generated simultaneously. Programmable

phase delay adjustment and programmable frame pulse

formatting is also available and both CMOS and differential

LVPECL outputs are provided. This means virtually any re-

quired frequency can be generated and adjusted as required,

eliminating the need for additional oscillators, external divid-

ers, clock multiplying PLLs or level translation devices.

Delivering leading integration, exibility, programmability

and performance, the ZL30117/22 can be implemented as

the sole timing and synchronization source for virtually any

line card deployed in multi-service provisioning and multi-

service switching platforms.

Advanced Mezzanine Card Synchronization