DATASHEET
551S REVISION A 03/18/15 1 ©2015 Integrated Device Technology, Inc.
Low Skew 1 to 4 Clock Buffer 551S
Description
The 551S is a low cost, high-speed single inp ut to four outp ut
clock buffer. The 551S has best in class Additive Phase Jitter
of sub 50fsec.
IDT makes many non-PLL and PLL based low skew output
devices as well as Zero Delay Buffers to synchronize clocks.
Contact IDT for all of your clocking needs.
Features
• Low additive phase jitter RMS: 50fs
• Extremely low skew outputs (50ps)
• Low cost clock buffer
• Packaged in 8-pin SOIC and 8-pin DFN, Pb-free
• Input/Output clock frequency up to 200 MHz
• Non-inverting output clock
• Ideal for network i ng clock s
• Operating Voltages: 1.8V to 3.3V
• Output Enable mode tri-states outputs
• Advanced, low power CMOS process
• Extended temperature range (-40°C to +105°C)
Block Diagram
Q1
ICLK
Q2
Q3
Q4
Output Enable
LOW SKEW 1 TO 4 CLOCK BUFFER 2 REVISION A 03/18/15
551S DATASHEET
Pin Assignment
Pin Descriptions
External Componen ts
A minimum number of external compone nts are required for proper operation. A decoupling capacitor of 0.01F should be
connected between VDD on pin 7 and GND o n pin 6, a s close to the device a s possible. A 33 series terminating resistor may
be used on each clock output if the trace is longer than 1 inch.
1
2
3
ICLK
4
Q1
Q2
VDD
Q3
GND
Q4
8
7
6
5
OE
8 Pin (150 mil) SOIC
1
2
3
ICLK
4
Q1
Q2
VDD
Q3
GND
Q4
8
7
6
5
OE
8-pin DFN
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 ICLK Input Clock input. Internal pull-up resistor.
2 Q1 Output Clock output 1.
3 Q2 Output Clock output 2.
4 Q3 Output Clock output 3.
5 Q4 Output Clock output 4.
6 GND Power Connect to ground.
7 VDD Power Connect +1.8V, +2.5V or +3.3V.
8 OE Input Output Enable. Tri-states outputs when low. Internal pull-up resistor.