Programming and Erasing Flash Memory
Devices Using the Keithley S530 Pulse
Generator Option
Introduction and Background
Normally, in parametric test, the instrument used most is the
Source Measurement Unit (SMU). The SMU allows supplying
a DC voltage or current to the device under test (DUT) and
simultaneously measuring the resultant voltage or current.
However, there are some cases where it’s necessary to apply a
voltage to the device in a time-controlled manner. Often, the
duration of these applied voltages must be on the order of a few
microseconds in order to prevent the DUT from over-heating or
being over-stressed. SMUs are not designed to output voltages
this quickly. Therefore, a different instrument is required: a
pulse generator.
A pulse generator allows outputting a voltage in a time-
controlled, time-accurate manner, including control over the
amount of voltage (pulse height), the duration of the pulse
(pulse width), as well as the voltage ramp rate (rise and fall
time). This type of instrument also provides the ability to control
the number of pulses that are output and even to synchronize
multiple pulses.
The Keithley S530 Parametric Test System offers a pulse
generator option that offers two to six channels of pulse outputs,
each of which is capable of outputting a maximum of ±40 VDC
with pulse durations from 100ns to 1s.
Typical applications for a pulse generator are preventing
device heating, time-controlled device stressing or charging,
generating clock signals, fuse testing, and setting and resetting
memory devices. This note describes how the pulse generator
option of the S530 Parametric Test System can be used to
characterize flash memory cells.
Flash Memory Basics
Flash memory is currently the dominant form of solid-state, non-
volatile memory technology. It is used in a wide range of devices
and applicationseverything from the common USB “thumb
drive” to smartphones, MP3 players, and digital cameras.
Flash memory is part of a class of MOS devices that use
floating gates. There are two types of flash cells: NOR and NAND.
In NOR technology, the storage cells can be programmed and
erased individually. Unfortunately, the storage densities for this
type of flash memory are comparatively low. In the second type,
NAND, its possible to write to the cells individually, but they
must be erased in blocks. NAND-type memory has a much higher
storage density and is by far the most dominant of the two types,
so this note will focus on NAND flash memory.
In addition to the floating gate, NAND flash memory cells
(
Figure 1
) usually have a control gate, drain, source, and bulk.
The memory cell is set (programmed) and reset (erased) by
applying or removing charge from the floating gate. Charge can
be applied or removed from the floating gate of any type of flash
memory cell via Fowler-Nordheim (FN) current tunneling or via
Hot Carrier Injection (HCI). In a normal CMOS transistor, both
of these mechanisms cause device degradation and are usually to
be avoided, but they are beneficial for flash memory. Moreover,
although FN tunneling and HCI are useful for programming and
erasing flash memory, they are also why flash memory cells have
a limited lifetime.
Sidewall Sidewall
Polysilicon control gate
Polysilicon floating gate
ONO Dielectric
Tunnel oxide
P substrate
N+ Source N+ Drain
Figure 1. NAND flash memory cell cross-section
When charge is applied to or removed from the floating gate,
the threshold voltage (V
T
) of the underlying transistor changes
(
Figure 2
). This threshold voltage change is what allows the flash
memory cell to be used as a memory storage device. Further,
once the charge is injected into or removed from the floating
gate, the floating gate remains in that state even after power is
removed, which means flash memory is non-volatile.
To program or erase a flash memory cell, a set of pulses are
applied. Pulses are used because applying a steady DC voltage
would cause the cell to be over-programmed or over-erased.
Once a cell is placed into one of these states, it cannot be set
to the opposite state, usually because the gate oxide has been
damaged in some way. The stimulus voltage must be applied
in a time-controlled manner, which is why a pulse generator
is required.
Number 3177
Application Note
Se ries
NAND flash cells fall into two categories: single-bit (logical
0/1) and multi-bit. As the names imply, in single-bit cells, each
storage location can hold only one bit; in multi-bit cells, each
storage location can hold multiple bits. In a single-bit cell, a two-
level pulse is required to set or reset the device, which results
in two distinct V
T
values (
Figure 3
). In multi-bit cells, multi-level
pulses are required to place the cell in each of its possible states,
which results in from four to eight possible V
T
values (
Figure 4
).
To program the cell using FN tunneling, a positive pulse is
applied to the gate, while the drain, source, and bulk voltages are
set to 0V (or grounded). This causes charge to be pushed into the
floating gate. To erase the cell via FN tunneling, a negative pulse
is applied to the gate (with the drain, source, and bulk terminals
set to 0V or connected to ground).
To use HCI, simultaneous pulses are applied to the gate
and drain (with the source and bulk grounded or set to zero).
This causes a field to appear in the transistor channel, thereby
creating the necessary hot carriers. The pulse height and polarity
of the gate pulse determines whether charge is applied to or
removed from the floating gate.
Usually, the threshold voltage is measured afterward to
ensure that the cell has indeed been programmed or erased. If
one programs and erases the cells thousands of time, one can
monitor its lifetime. (For the sake of simplicity, this note focuses
only on single-bit flash memory cells.)
Measurement Considerations
A parametric test system is oriented primarily toward performing
accurate DC measurements. Therefore, the switch matrix and
relays typically used are designed and optimized to ensure good
DC performance, such as low leakage current, minimal offset
voltages and currents, and low resistances. The optimization of
DC performance usually comes at some cost to the systems AC
performance.
In contrast, pulses are essentially AC signals. A square pulse
train can be represented by the Fourier expansion as an infinite
series of sinusoids:
f
pulse
(t) = t
n=1
sin
()
()
2
T
nπ
πnτ 2πn
TT
+
τ
cos
Σ
where: T is the period, τ the pulse width, and t is the total time.
Because the switching subsystem of the parametric tester is
optimized for DC, it has a limited bandwidth (less than 30MHz).
Sidewall
Sidewall
Program charge transfer
Polysilicon control gate
Polysilicon floating gate
ONO Dielectric
Tunnel oxide
P substrate
N+ Source
0V 0V 0V 0V
N+ Drain
Sidewall
Erase charge transfer
Polysilicon control gate
ONO Dielectric
P substrate
N+ Source N+ Drain
Sidewall
Polysilicon floating gate
Tunnel oxide
Figure 2. Charge transfer in a NAND flash cell
V
T
(volts)
10
Distribution
Figure 3. Single-bit V
T
distribution
V
T
(volts)
11 10 01 00
Distribution
Figure 4. Multi-bit V
T
distribution