Document Number: 90386
www.vishay.com
S11-1045-Rev. C, 30-May-11 1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Power MOSFET
IRL540S, SiHL540S
Vishay Siliconix
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• Surface Mount
• Available in Tape and Reel
• Dynamic dV/dt Rating
• Repetitive Avalanche Rated
• Logic-Level Gate Drive
•R
DS(on)
Specified at V
GS
= 4 V and 5 V
• 175 °C Operating Temperature
• Compliant to RoHS Directive 2002/95/EC
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D
2
PAK (TO-263) is a surface mount power package
capable of accommodating die size up to HEX-4. It provides
the highest power capability and the lowest possible
on-resistance in any existing surface mount package. The
D
2
PAK (TO-263) is suitable for high current applications
because of its low internal connection resistance and can
dissipate up to 2.0 W in a typical surface mount application.
Note
a. See device orientation.
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V
DD
= 25 V, starting T
J
= 25 °C, L = 841 μH, R
g
= 25 , I
AS
= 28 A (see fig. 12).
c. I
SD
28 A, dI/dt 170 A/μs, V
DD
V
DS
, T
J
175 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
PRODUCT SUMMARY
V
DS
(V) 100
R
DS(on)
()V
GS
= 5 V 0.077
Q
g
(Max.) (nC) 64
Q
gs
(nC) 9.4
Q
gd
(nC) 27
Configuration Single
N-Channel MOSFET
G
D
S
D
2
PAK (TO-263)
G
D
S
ORDERING INFORMATION
Package
D
2
PAK (TO-263) D
2
PAK (TO-263)
Lead (Pb)-free and Halogen-free SiHL540S-GE3
SiHL540STRL-GE3
a
Lead (Pb)-free
IRL540SPbF
IRL540STRLPbF
a
SiHL540S-E3
SiHL540STL-E3
a
ABSOLUTE MAXIMUM RATINGS (T
C
= 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage
V
DS
100
V
Gate-Source Voltage
V
GS
± 10
Continuous Drain Current
V
GS
at 5 V
T
C
= 25 °C
I
D
28
A
T
C
= 100 °C
20
Pulsed Drain Current
a
I
DM
110
Linear Derating Factor 1.0
W/°C
Linear Derating Factor (PCB Mount)
e
0.025
Single Pulse Avalanche Energy
b
E
AS
440 mJ
Avalanche Current
a
I
AR
28 A
Repetiitive Avalanche Energy
a
E
AR
15 mJ
Maximum Power Dissipation
T
C
= 25 °C
P
D
150
W
Maximum Power Dissipation (PCB Mount)
e
T
A
= 25 °C
3.7
Peak Diode Recovery dV/dt
c
dV/dt 5.5 V/ns
Operating Junction and Storage Temperature Range
T
J
, T
stg
- 55 to + 175
°C
Soldering Recommendations (Peak Temperature) for 10 s
300
d
* Pb containing terminations are not RoHS compliant, exemptions may apply
www.vishay.com Document Number: 90386
2 S11-1045-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRL540S, SiHL540S
Vishay Siliconix
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 μs; duty cycle 2 %.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient R
thJA
-62
°C/W
Maximum Junction-to-Ambient
(PCB Mount)
a
R
thJA
-40
Maximum Junction-to-Case (Drain) R
thJC
-1.0
SPECIFICATIONS (T
J
= 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage V
DS
V
GS
= 0, I
D
= 250 μA 100 - - V
V
DS
Temperature Coefficient V
DS
/T
J
Reference to 25 °C, I
D
= 1 mA - 0.12 - V/°C
Gate-Source Threshold Voltage V
GS(th)
V
DS
= V
GS
, I
D
= 250 μA 1.0 - 2.0 V
Gate-Source Leakage I
GSS
V
GS
= ± 10 V - - ± 100 nA
Zero Gate Voltage Drain Current I
DSS
V
DS
= 100 V, V
GS
= 0 V - - 25
μA
V
DS
= 80 V, V
GS
= 0 V, T
J
= 150 °C - - 250
Drain-Source On-State Resistance R
DS(on)
V
GS
= 5 V I
D
= 17 A
b
- - 0.077
V
GS
= 4 V I
D
= 14 A
b
- - 0.11
Forward Transconductance g
fs
V
DS
= 50 V, I
D
= 17 A
b
12 - - S
Dynamic
Input Capacitance C
iss
V
GS
= 0 V,
V
DS
= 25 V,
f = 1.0 MHz, see fig. 5
- 2200 -
pFOutput Capacitance C
oss
- 560 -
Reverse Transfer Capacitance C
rss
- 140 -
Total Gate Charge Q
g
V
GS
= 5 V
I
D
= 28 A, V
DS
= 80 V,
see fig. 6 and 13
b
--64
nC Gate-Source Charge Q
gs
--9.4
Gate-Drain Charge Q
gd
--27
Turn-On Delay Time t
d(on)
V
DD
= 50 V, I
D
= 28 A,
R
g
= 9.0 , R
D
= 1.7 , see fig. 10
b
-8.5-
ns
Rise Time t
r
- 170 -
Turn-Off Delay Time t
d(off)
-35-
Fall Time t
f
-80-
Internal Drain Inductance L
D
Between lead,
6 mm (0.25") from
package and center of
die contact
-4.5-
nH
Internal Source Inductance L
S
-7.5-
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current I
S
MOSFET symbol
showing the
integral reverse
p - n junction diode
--28
A
Pulsed Diode Forward Current
a
I
SM
- - 110
Body Diode Voltage V
SD
T
J
= 25 °C, I
S
= 28 A, V
GS
= 0 V
b
--2.5V
Body Diode Reverse Recovery Time t
rr
T
J
= 25 °C, I
F
= 28 A, dI/dt = 100 A/μs
b
- 200 260 ns
Body Diode Reverse Recovery Charge Q
rr
-1.72.9μC
Forward Turn-On Time t
on
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
and L
D
)
D
S
G
S
D
G